Patents by Inventor Ming-Te Tsai

Ming-Te Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240081081
    Abstract: A ferroelectric memory device and a semiconductor die are provided. The ferroelectric memory device includes a gate electrode; a channel layer, overlapped with the gate electrode; source/drain contacts, in contact with separate ends of the channel layer; a ferroelectric layer, lying between the gate electrode and the channel layer; and a first insertion layer, extending in between the ferroelectric layer and the channel layer, and comprising a metal carbonitride or a metal nitride.
    Type: Application
    Filed: January 10, 2023
    Publication date: March 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya-Ling Lee, Chung-Te Lin, Han-Ting Tsai, Wei-Gang Chiu, Yen-Chieh Huang, Ming-Yi Yang
  • Publication number: 20160132535
    Abstract: The present invention provides an acceleration method for database using index value operation and mixed-mode leveled cache. While building a database, an algorithm is adopted for operating a plurality of field conditions and giving an index value. At least a file record in the database satisfying the plurality of field conditions is related to the index value. While querying, the input plurality of field conditions are operated using the algorithm, giving the index value. According to the index value, the file records in the database satisfying the plurality of field conditions are listed. Thereby, the time for comparing the plurality of fields can be saved.
    Type: Application
    Filed: July 24, 2015
    Publication date: May 12, 2016
    Inventors: YU-JUNG CHENG, YUN-TE LIN, YUNG-HSIANG HUANG, MING-TE TSAI, YI-HAO HSIAO, FANG-PANG LIN
  • Publication number: 20140231001
    Abstract: A multi-layered structure includes a first carrier, a second carrier, a first substrate and a second substrate. The first and second substrates are disposed between the first and second carriers. A panel sealant and a dummy sealant are positioned between the first and second substrates, wherein the panel sealant surrounds a display panel unit, and the dummy sealant is outside the panel sealant and surrounds the panel sealant. The dummy sealant to the peripheries of the first and the second substrates creates a gap. Then, glue seeps into the gap, and is cured subsequently. Next, a cutting step is performed on the first bonding structure (between the first substrate and the first carrier) and the second bonding structure (between the second substrate and the second carrier) to generate a cutting notch, respectively. The first and second carriers are peeled off from the corresponding cutting notches.
    Type: Application
    Filed: January 20, 2014
    Publication date: August 21, 2014
    Applicant: Innolux Corporation
    Inventor: Ming-Te Tsai