Abstract: A method according to the present disclosure includes receiving a workpiece that includes a gate structure, a first gate spacer feature, a second gate spacer feature, a gate-top dielectric feature over the gate structure, the first gate spacer feature and the second gate spacer feature, a first source/drain feature over a first source/drain region, a second source/drain feature over a second source/drain region, a first dielectric layer over the first source/drain feature, and a second dielectric layer over the second source/drain feature. The method further includes replacing a top portion of the first dielectric layer with a first hard mask layer, forming a second hard mask layer over the first hard mask layer while the second dielectric layer is exposed, etching the second dielectric layer to form a source/drain contact opening and to expose the second source/drain feature, and forming a source/drain contact over the second source/drain feature.

Abstract: A semiconductor device includes a first diode having a first cathode and a first anode, wherein the first cathode is floating. The semiconductor device includes a second diode having a second cathode and a second anode, wherein the first anode is coupled to the second anode with the second cathode connected to a first supply voltage. The semiconductor device includes a third diode having a third cathode and a third anode, wherein the third cathode is connected to the first anode at an input/output pin, with the third anode connected to a second supply voltage. The second anode is coupled to a circuit that is powered by the first supply voltage and the second supply voltage. The first diode has a first size and the second diode has a second size, and the first size is substantially greater than the second size.

Abstract: A computing circuit with a de-identified architecture, a data computing method, a data processing system, and a data de-identification method are provided. The computing circuit includes an arithmetic array and a de-identification circuit. The computing circuit may perform an accumulation operation on input data to generate accumulated data by the arithmetic array. The de-identification circuit has an analog offset error determined based on an analog physical unclonable function. The computing circuit may operate the accumulated data according to the analog offset error to generate de-identification data by the de-identification circuit. It can not only provide the analog offset error through the transistors in the de-identification circuit, but also be combined with obfuscated code settings to dynamically adjusting the degree of de-identification of data.

Abstract: Disclosed are a method and a device for identifying full-section excavation parameters of large-section tunnel with broken surrounding rock, which is capable of solving the problem of inaccurate arrangement of blasting hole points in tunnel excavation engineering, including following steps: establishing a three-dimensional finite element model based on a blasting section design of a tunnel; performing a simulation with the three-dimensional finite element model based on blasting design parameters to obtain blasting quality parameters; selecting a group closest to a preset quality parameter from multiple groups of the blasting design parameters as target blasting design parameters, wherein the preset quality parameter is an acceptance grade standard of the tunnel; obtaining first thermal imaging information of a first hot spot of a surface to be blasted; calibrating actual hole spacing parameters based on the first thermal imaging information and the target blasting design parameters.

Abstract: Various embodiments of the present application are directed towards an integrated chip structure. The integrated chip structure includes a bottom electrode over a substrate, a top electrode over the bottom electrode, and a capacitor insulator structure between the bottom electrode and the top electrode. The capacitor insulator structure includes a first dielectric layer, a second dielectric layer over the first dielectric layer, and a third dielectric layer over the second dielectric layer. The first dielectric layer includes a first dielectric material. The second dielectric layer includes a second dielectric material that is different than the first dielectric material. The second dielectric material is an amorphous solid. The third dielectric layer includes the first dielectric material.

Abstract: A method includes receiving a carrier, the carrier including a carrier body, a first filter, and a housing securing the first filter to the carrier body. The method further includes uninstalling the housing from the carrier, replacing the first filter with a second filter, reinstalling the housing on the carrier body, and inspecting the second filter. Inspecting the second filter includes using an automatic inspection mechanism to detect surface flatness of the second filter.

Abstract: The present invention relates to an ultrasound image enhancement processing system and method thereof. The ultrasound image enhancement processing system includes at least one first ultrasound device and at least one server apparatus. The server apparatus receives a first ultrasound original image file, processes the first ultrasound original image file through a speckle reduction algorithm to generate a first processed image file, and performs a deep learning training on the first ultrasound original image file and the first processed image file to generate a first neural network model. The first neural network learning module is used to output a first speckle reduction enhancement image file. The image content of the first speckle reduction enhancement image file is approximating to the image content of the first processed image file.

Abstract: There is provided a wearable device including at least one light source, a light sensor and a processor. The processor generates a peak interval plot according to one of at least two light detection signals detected by the light sensor when the at least one light source emits light, and generates an oxygen saturation plot according to two of the one of at least two light detection signals detected by the light sensor when the at least one emits light. The processor further determines an Apnea Hypopnea Index (AHI) score according to the peak interval plot, determines an Oxygen Desaturation Index (ODI) score according to the oxygen saturation plot and fits an obstructive sleep apnea level index corresponding to the AHI score and the ODI score.

Abstract: An improved integrated coil structure includes an iron core body and first, second, third, and fourth coils. The iron core body includes first and second wire-winding portions. The iron core body is provided with first and second flanges respectively at two sides thereof and a third flange arranged between the first and second flanges. First and second electrodes are arranged on the first flange. Third and fourth electrodes are arranged on the second flange. Fifth, sixth, and seventh electrodes are arranged on the third flange. Two terminals of the first coil are electrically connected with the first and fifth electrodes. Two terminals of the second coil are electrically connected with the second and seventh electrodes. Two terminals of the third coil are electrically connected with the third and sixth electrodes. Two terminals of the fourth coil are electrically connected with the fourth and seventh electrodes.

Abstract: A method includes: forming a bottom electrode over a substrate; depositing a first seed layer over the bottom electrode, the first seed layer having an amorphous crystal phase; performing a first surface treatment on the first seed layer, wherein after the first surface treatment the first seed layer includes at least one of a tetragonal crystal phase and an orthorhombic crystal phase; depositing a dielectric layer over the bottom electrode adjacent to the first seed layer; depositing an upper layer over the dielectric layer; and performing a thermal operation on the dielectric layer to thereby convert the dielectric layer into a ferroelectric layer.

Abstract: A data transmission method, a data transmission device, non-transitory computer readable medium, and a chip for sidelink communication.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a bottom electrode over a substrate. A dielectric layer is formed on the bottom electrode. A first top electrode layer is deposited on the dielectric layer by a first deposition process. A diffusion barrier layer is deposited on the first top electrode layer by a second deposition process different from the first deposition process. A second top electrode layer is deposited on the diffusion barrier layer by a third deposition. The third deposition process is the same as the first deposition process.

Abstract: The present application discloses a channel quality feedback method and apparatus. The method includes: a first terminal receives indication information sent by a second terminal, where the indication information is used to instruct the first terminal to send a channel quality indicator and/or a rank indicator to the second terminal. The first terminal generates a media access control layer control element (MAC CE), where the MAC CE includes the channel quality indicator and/or the rank indicator. The first terminal sends the MAC CE to the second terminal. The first terminal sends the MAC CE including the channel quality indicator and/or the rank indicator to the second terminal, so that the channel quality feedback of the first terminal to the second terminal is completed through the channel quality indicator and/or the rank indicator, thereby realizing the channel quality feedback between terminals.

Abstract: The present application relates to the field of wireless communications. Disclosed are a resource selection method and device, a terminal, and a medium. The method comprises: determining a resource monitoring window, wherein the resource monitoring window comprises some of time slots before a time slot m where a selected resource is located; and when the monitoring result of the resource monitoring window is that a resource conflict occurs between the selected resource and a reserved resource of a second terminal, performing resource reselection for the selected resource. In the present application, the determined resource monitoring window only comprises some of the time slots before the time slot m where the selected resource is located, instead of all the time slots, and therefore, in a monitoring process of resource reselection, the time required for monitoring is reduced, and the power consumption of a first terminal is reduced.

Abstract: A manufacturing method of a memory structure including the following steps is provided. A substrate is provided. The substrate includes a memory array region. A bit line structure is formed in the memory array region. The bit line structure is located on the substrate. A contact structure is formed in the memory array region. The contact structure is located on the substrate on one side of the bit line structure. A stop layer is formed in the memory array region. The stop layer is located above the bit line structure. A capacitor structure is formed in the memory array region. The capacitor structure passes through the stop layer and is electrically connected to the contact structure. The bottom surface of the capacitor structure is lower than the bottom surface of the stop layer.

Abstract: A system for bonding films includes a first film, a second film having a plurality of elements, a bonding roller, and a deformable roller having a deformable outer layer. The stiffness of the second film is less than that of the first film. By using the system, the deformable outer layer of the deformable roller produces enough deformation during bonding films to fill the area not covered by the plurality of elements on the second film. Therefore, the second film without sufficient stiffness and the first film can be bonded with each other to produce a composite film without wrinkles. A method for preparing a composite film using the system is also disclosed.

Abstract: Present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor fin and a metal gate. The semiconductor fin has a first portion and a second portion over the first portion. A height of the second portion is greater than a width of the second portion. The metal gate has a bottom portion, an upper portion, and a lateral portion connecting the bottom portion and the upper portion. The bottom portion is between the first portion and the second portion of the semiconductor fin, and the upper portion is over the second portion of the semiconductor fin.

Abstract: A system and computer-implemented method include receiving a request for allocating graphical processing unit (GPU) resources for performing an operation. The request includes metadata identifying a client identifier (ID) associated with a client, throughput, and latency of the operation. A resource limit is determined for performing the operation based on the metadata. Attributes associated with each GPU resource of a plurality of GPU resources available for assignment are obtained. The attribute is analyzed that is associated with each GPU resource with respect to the resource limit. A set of GPU resources is identified from the plurality of GPU resources based on the analysis. A dedicated AI cluster is generated by patching the set of GPU resources within a single cluster. The dedicated AI cluster reserves a portion of a computation capacity of a computing system for a period of time and the dedicated AI cluster is allocated to the client associated with the client ID.

Abstract: A method for manufacturing an electronic device is provided. The method includes providing a first substrate. The method further includes forming a bank layer on the first substrate. The bank layer includes a bank wall and a first opening, and the first opening adjacent to the bank wall. The method further includes forming a light conversion layer in the first opening. The method further includes forming a spacer on the bank wall. The method further includes providing a second substrate. The method further includes transferring a plurality of electronic units to the second substrate. The method further includes overlapping the first substrate and second substrate, so that the spacer is located between the first substrate and the second substrate.

Abstract: A display panel includes a first substrate and a shading structure. The shading structure is disposed on the first substrate. The shading structure includes a plurality of first parts and a second part. One of the plurality of first parts extends along a first direction. The second part protrudes from the one of the plurality of first part. Wherein the second part is separated from another one of the plurality of first parts adjacent to the one of the plurality of first parts, and the another one of the plurality of first parts extends along the first direction.