Patents by Inventor Ming Ting Lin
Ming Ting Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240135990Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.Type: ApplicationFiled: December 28, 2023Publication date: April 25, 2024Applicant: Winbond Electronics Corp.Inventors: Ming-Che Lin, Min-Chih Wei, Ping-Kun Wang, Yu-Ting Chen, Chih-Cheng Fu, Chang-Tsung Pai
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Publication number: 20240136183Abstract: A photo resist layer is used to protect a dielectric layer and conductive elements embedded in the dielectric layer when patterning an etch stop layer underlying the dielectric layer. The photo resist layer may further be used to etch another dielectric layer underlying the etch stop layer, where etching the next dielectric layer exposes a contact, such as a gate contact. The bottom layer can be used to protect the conductive elements embedded in the dielectric layer from a wet etchant used to etch the etch stop layer.Type: ApplicationFiled: January 2, 2024Publication date: April 25, 2024Inventors: Yu-Shih Wang, Hong-Jie Yang, Chia-Ying Lee, Po-Nan Yeh, U-Ting Chiu, Chun-Neng Lin, Ming-Hsi Yeh, Kuo-Bin Huang
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Patent number: 11961796Abstract: A package comprises at least one first device die, and a redistribution line (RDL) structure having the at least one first device die bonded thereto. The RDL structure comprises a plurality of dielectric layers, and a plurality of RDLs formed through the plurality of dielectric layers. A trench is defined proximate to axial edges of the RDL structure through each of the plurality of dielectric layers. The trench prevents damage to portions of the RDL structure located axially inwards of the trench.Type: GrantFiled: August 30, 2021Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yueh-Ting Lin, Hua-Wei Tseng, Ming Shih Yeh, Der-Chyang Yeh
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Patent number: 11963347Abstract: A memory device includes a transistor, an anti-fuse element, a source/drain contact, a first gate via, and a second gate via. The transistor is over a substrate. The anti-fuse element is over the substrate and is connected to the transistor in series. The source/drain contact is connected to a source/drain region of the transistor. The first gate via is connected to a first gate structure of the transistor. The first gate structure of the transistor extends along a first direction in a top view. The second gate via is connected to a second gate structure of the anti-fuse element. The second gate via is between the first gate via and the source/drain contact along the first direction in the top view.Type: GrantFiled: April 21, 2023Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chiung-Ting Ou, Ming-Yih Wang, Jian-Hong Lin
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Patent number: 11948820Abstract: The present invention provides a latching guide structure arranged inside a door of semiconductor carrier. The latching guide structure comprises an upper latching part, a lower latching part, at least one elastic unit and a driver. Moreover, a first guiding portion of the upper latching part is matched with a second guiding portion of the lower latching part, therefore to define the installation space for the at least one elastic unit. On the other hand, the driver simultaneously actuates an upper actuating unit of the first guiding portion and a lower actuating unit of the second guiding portion to linearly move in reverse direction therebetween. The range of the linear motion of the upper actuating unit and the lower actuating unit represents the compression or extension of the at least one elastic unit, determining to control the open/close status of the upper latching part and the lower latching part.Type: GrantFiled: November 28, 2022Date of Patent: April 2, 2024Assignee: GUDENG PRECISION INDUSTRIAL CO., LTD.Inventors: Ming-Chien Chiu, Chih-Ming Lin, Cheng-Han Chou, Po-Ting Lee
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Publication number: 20240105481Abstract: The present invention provides a latching guide structure arranged inside a door of semiconductor carrier. The latching guide structure comprises an upper latching part, a lower latching part, at least one elastic unit and a driver. Moreover, a first guiding portion of the upper latching part is matched with a second guiding portion of the lower latching part, therefore to define the installation space for the at least one elastic unit. On the other hand, the driver simultaneously actuates an upper actuating unit of the first guiding portion and a lower actuating unit of the second guiding portion to linearly move in reverse direction therebetween. The range of the linear motion of the upper actuating unit and the lower actuating unit represents the compression or extension of the at least one elastic unit, determining to control the open/close status of the upper latching part and the lower latching part.Type: ApplicationFiled: November 28, 2022Publication date: March 28, 2024Inventors: MING-CHIEN CHIU, CHIH-MING LIN, CHENG-HAN CHOU, PO-TING LEE
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Publication number: 20240081081Abstract: A ferroelectric memory device and a semiconductor die are provided. The ferroelectric memory device includes a gate electrode; a channel layer, overlapped with the gate electrode; source/drain contacts, in contact with separate ends of the channel layer; a ferroelectric layer, lying between the gate electrode and the channel layer; and a first insertion layer, extending in between the ferroelectric layer and the channel layer, and comprising a metal carbonitride or a metal nitride.Type: ApplicationFiled: January 10, 2023Publication date: March 7, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ya-Ling Lee, Chung-Te Lin, Han-Ting Tsai, Wei-Gang Chiu, Yen-Chieh Huang, Ming-Yi Yang
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Patent number: 11916131Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.Type: GrantFiled: November 4, 2020Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: De-Fang Chen, Teng-Chun Tsai, Cheng-Tung Lin, Li-Ting Wang, Chun-Hung Lee, Ming-Ching Chang, Huan-Just Lin
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Patent number: 8459480Abstract: A case structure and a method for pre-forming the same are described. The pre-forming method includes the following steps. A first case body and a second case body are supplied. Two side plates of the second case body are bent, such that the two side plates respectively form an initial angle with the bottom plate. The second case body is disposed in the first case body. The two side plates are pulled to respectively come close to two side walls of the first case body, such that the bottom plate forms a curved surface in the first case body. When having an object disposed therein, the case structure overcomes a downward pressure generated by the object through the curved surface, thereby preventing the first case body and the second case body from sagging out of the case structure.Type: GrantFiled: May 4, 2010Date of Patent: June 11, 2013Assignee: Inventec CorporationInventors: Kuei-Hua Chen, Jung-Lung Chen, Ming-Ting Lin
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Publication number: 20110273069Abstract: A case structure and a method for pre-forming the same are described. The pre-forming method includes the following steps. A first case body and a second case body are supplied. Two side plates of the second case body are bent, such that the two side plates respectively form an initial angle with the bottom plate. The second case body is disposed in the first case body. The two side plates are pulled to respectively come close to two side walls of the first case body, such that the bottom plate forms a curved surface in the first case body. When having an object disposed therein, the case structure overcomes a downward pressure generated by the object through the curved surface, thereby preventing the first case body and the second case body from sagging out of the case structure.Type: ApplicationFiled: May 4, 2010Publication date: November 10, 2011Applicant: INVENTEC CORPORATIONInventors: Kuei Hua Chen, Jung Lung Chen, Ming Ting Lin