Patents by Inventor Ming-Tse Lin
Ming-Tse Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12148723Abstract: A structure of semiconductor device is provided, including a first circuit structure, formed on a first substrate. A first test pad is disposed on the first substrate. A second circuit structure is formed on a second substrate. A second test pad is disposed on the second substrate. A first bonding pad of the first circuit structure is bonded to a second bonding pad of the second circuit structure. One of the first test pad and the second test pad is an inner pad while another one of the first test pad and the second test pad is an outer pad, wherein the outer pad surrounds the inner pad.Type: GrantFiled: December 7, 2022Date of Patent: November 19, 2024Assignee: United Microelectronics Corp.Inventors: Zhirui Sheng, Hui-Ling Chen, Chung-Hsing Kuo, Chun-Ting Yeh, Ming-Tse Lin, Chien En Hsu
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Patent number: 12068234Abstract: A semiconductor structure includes an interposer substrate, an electronic device formed in a device region of the interposer substrate, a guard ring formed in the interposer substrate and surrounding the device region, a first redistribution layer on an upper surface of the interposer substrate and covering the device region and the guard ring, and a chip disposed on the first redistribution layer and overlapping the device region.Type: GrantFiled: May 23, 2023Date of Patent: August 20, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Hung Chen, Ming-Tse Lin
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Publication number: 20240119693Abstract: A method of an optical sensor device includes: providing an optical sensor for receiving reflected light associated with a light emission unit to generate at least one sensed image; using a first exposure setting to make the optical sensor generate a first frame data during a first frame time period of a frame; when performing an exposure adjustment operation, using a second exposure setting to make the optical sensor generate a second frame data during a second time period of the frame neighbor to the first frame time period of the frame; and, generating a normalized digital signal corresponding to the first frame data based on the relation between the first frame data and the second frame data.Type: ApplicationFiled: September 25, 2022Publication date: April 11, 2024Applicant: PixArt Imaging Inc.Inventor: Ming-Tse Lin
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Publication number: 20230290719Abstract: A semiconductor structure includes an interposer substrate, an electronic device formed in a device region of the interposer substrate, a guard ring formed in the interposer substrate and surrounding the device region, a first redistribution layer on an upper surface of the interposer substrate and covering the device region and the guard ring, and a chip disposed on the first redistribution layer and overlapping the device region.Type: ApplicationFiled: May 23, 2023Publication date: September 14, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chun-Hung Chen, Ming-Tse Lin
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Patent number: 11699646Abstract: A semiconductor structure includes an interposer substrate having an upper surface, a lower surface opposite to the upper surface, and a device region. A first redistribution layer is formed on the upper surface of the interposer substrate. A guard ring is formed in the interposer substrate and surrounds the device region. At least a through-silicon via (TSV) is formed in the interposer substrate. An end of the guard ring and an end of the TSV that are near the upper surface of the interposer substrate are flush with each other, and are electrically connected to the first redistribution layer.Type: GrantFiled: September 13, 2022Date of Patent: July 11, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Hung Chen, Ming-Tse Lin
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Publication number: 20230101900Abstract: A structure of semiconductor device is provided, including a first circuit structure, formed on a first substrate. A first test pad is disposed on the first substrate. A second circuit structure is formed on a second substrate. A second test pad is disposed on the second substrate. A first bonding pad of the first circuit structure is bonded to a second bonding pad of the second circuit structure. One of the first test pad and the second test pad is an inner pad while another one of the first test pad and the second test pad is an outer pad, wherein the outer pad surrounds the inner pad.Type: ApplicationFiled: December 7, 2022Publication date: March 30, 2023Applicant: United Microelectronics Corp.Inventors: Zhirui Sheng, Hui-Ling Chen, Chung-Hsing Kuo, Chun-Ting Yeh, Ming-Tse Lin, Chien En Hsu
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Patent number: 11569188Abstract: A semiconductor device, including a first semiconductor substrate and a second semiconductor substrate, is provided. A first bonding structure is located on the first semiconductor substrate and includes a first pad having an elongated shape. A second bonding structure is located on the second semiconductor substrate and includes a second pad having an elongated shape. The first semiconductor substrate is bonded to the second semiconductor substrate by bonding the first bonding structure and the second bonding structure. The first pad is bonded to the second pad, and an extension direction of the first pad is different from an extension direction of the second pad.Type: GrantFiled: July 28, 2021Date of Patent: January 31, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chung-Hsing Kuo, Chun-Ting Yeh, Ming-Tse Lin
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Patent number: 11557558Abstract: A structure of semiconductor device is provided, including a first circuit structure, formed on a first substrate. A first test pad is disposed on the first substrate. A second circuit structure is formed on a second substrate. A second test pad is disposed on the second substrate. A first bonding pad of the first circuit structure is bonded to a second bonding pad of the second circuit structure. One of the first test pad and the second test pad is an inner pad while another one of the first test pad and the second test pad is an outer pad, wherein the outer pad surrounds the inner pad.Type: GrantFiled: August 4, 2020Date of Patent: January 17, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Zhirui Sheng, Hui-Ling Chen, Chung-Hsing Kuo, Chun-Ting Yeh, Ming-Tse Lin, Chien En Hsu
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Publication number: 20230005833Abstract: A semiconductor structure includes an interposer substrate having an upper surface, a lower surface opposite to the upper surface, and a device region. A first redistribution layer is formed on the upper surface of the interposer substrate. A guard ring is formed in the interposer substrate and surrounds the device region. At least a through-silicon via (TSV) is formed in the interposer substrate. An end of the guard ring and an end of the TSV that are near the upper surface of the interposer substrate are flush with each other, and are electrically connected to the first redistribution layer.Type: ApplicationFiled: September 13, 2022Publication date: January 5, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chun-Hung Chen, Ming-Tse Lin
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Publication number: 20220415836Abstract: A semiconductor device, including a first semiconductor substrate and a second semiconductor substrate, is provided. A first bonding structure is located on the first semiconductor substrate and includes a first pad having an elongated shape. A second bonding structure is located on the second semiconductor substrate and includes a second pad having an elongated shape. The first semiconductor substrate is bonded to the second semiconductor substrate by bonding the first bonding structure and the second bonding structure. The first pad is bonded to the second pad, and an extension direction of the first pad is different from an extension direction of the second pad.Type: ApplicationFiled: July 28, 2021Publication date: December 29, 2022Applicant: United Microelectronics Corp.Inventors: Chung-Hsing Kuo, Chun-Ting Yeh, Ming-Tse Lin
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Publication number: 20220384376Abstract: A package structure of a semiconductor device includes a first substrate, a second substrate, and a bonding layer. The bonding layer bonds the first substrate and the second substrate. The bonding layer includes an inner bonding pad pattern and an outer bonding pad pattern formed in a dielectric layer. The outer bonding pad pattern surrounds the inner bonding pad pattern. The outer bonding pad pattern includes first bonding pads, the inner bonding pad pattern includes second bonding pads, a density of the first bonding pads is greater than that of the second bonding pads. The first bonding pads of the outer bonding pad pattern is distributed to form a plurality of pad rings surrounding the inner bonding pad pattern, and the first bonding pads of the plurality of pad rings are aligned in a horizontal direction or a vertical direction.Type: ApplicationFiled: August 4, 2022Publication date: December 1, 2022Applicant: United Microelectronics Corp.Inventors: Ming-Tse Lin, Chung-Hsing Kuo, Hui-Ling Chen
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Patent number: 11482485Abstract: A semiconductor structure is disclosed. The semiconductor structure includes an interposer substrate having an upper surface and a lower surface that is opposite to the upper surface. A guard ring is formed in the interposer substrate and surrounds a device region of the interposer substrate. At least a through-silicon via is formed in the interposer substrate. An end of the guard ring and an end of the through-silicon via that are near the upper surface of the interposer substrate are flush with each other.Type: GrantFiled: October 18, 2020Date of Patent: October 25, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Hung Chen, Ming-Tse Lin
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Patent number: 11450633Abstract: A package structure of a semiconductor device includes a first substrate, a second substrate, and a bonding layer. The bonding layer bonds the first substrate and the second substrate. The bonding layer includes an inner bonding pad pattern and an outer bonding pad pattern formed in a dielectric layer. The outer bonding pad pattern surrounds the inner bonding pad pattern. A first bonding pad density of the outer bonding pad pattern is greater than a second bonding pad density of the inner bonding pad pattern.Type: GrantFiled: February 4, 2020Date of Patent: September 20, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ming-Tse Lin, Chung-Hsing Kuo, Hui-Ling Chen
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Publication number: 20220084928Abstract: A semiconductor structure is disclosed. The semiconductor structure includes an interposer substrate having an upper surface and a lower surface that is opposite to the upper surface. A guard ring is formed in the interposer substrate and surrounds a device region of the interposer substrate. At least a through-silicon via is formed in the interposer substrate. An end of the guard ring and an end of the through-silicon via that are near the upper surface of the interposer substrate are flush with each other.Type: ApplicationFiled: October 18, 2020Publication date: March 17, 2022Inventors: Chun-Hung Chen, Ming-Tse Lin
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Publication number: 20220005775Abstract: A structure of semiconductor device is provided, including a first circuit structure, formed on a first substrate. A first test pad is disposed on the first substrate. A second circuit structure is formed on a second substrate. A second test pad is disposed on the second substrate. A first bonding pad of the first circuit structure is bonded to a second bonding pad of the second circuit structure. One of the first test pad and the second test pad is an inner pad while another one of the first test pad and the second test pad is an outer pad, wherein the outer pad surrounds the inner pad.Type: ApplicationFiled: August 4, 2020Publication date: January 6, 2022Applicant: United Microelectronics Corp.Inventors: Zhirui Sheng, Hui-Ling Chen, Chung-Hsing Kuo, Chun-Ting Yeh, Ming-Tse Lin, Chien En Hsu
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Patent number: 11164822Abstract: A structure of semiconductor device is provided. The structure includes a first bonding pattern, formed on a first substrate. A first grating pattern is disposed on the first substrate, having a plurality of first bars extending along a first direction. A second bonding pattern is formed on a second substrate. A second grating pattern, disposed on the second substrate, having a plurality of second bars extending along the first direction. The first bonding pattern is bonded to the second bonding pattern. One of the first grating pattern and the second grating pattern is stacked over and overlapping at the first direction with another one of the first grating pattern and the second grating pattern. A first gap between adjacent two of the first bars is different from a second gap between adjacent two of the second bars.Type: GrantFiled: September 28, 2020Date of Patent: November 2, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chung-Hsing Kuo, Chun-Ting Yeh, Ming-Tse Lin, Hui-Ling Chen, Chien-Ming Lai
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Publication number: 20210202418Abstract: A package structure of a semiconductor device includes a first substrate, a second substrate, and a bonding layer. The bonding layer bonds the first substrate and the second substrate. The bonding layer includes an inner bonding pad pattern and an outer bonding pad pattern formed in a dielectric layer. The outer bonding pad pattern surrounds the inner bonding pad pattern. A first bonding pad density of the outer bonding pad pattern is greater than a second bonding pad density of the inner bonding pad pattern.Type: ApplicationFiled: February 4, 2020Publication date: July 1, 2021Applicant: United Microelectronics Corp.Inventors: MING-TSE LIN, Chung-Hsing Kuo, Hui-Ling Chen
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Publication number: 20210057368Abstract: The present disclosure provides a manufacturing method of a die-stack structure including follow steps. A first wafer including a first die is provided, wherein the first die includes a first substrate material layer, a first interconnect structure, and a first pad, and the first interconnect structure and the first pad are formed on the first substrate material layer in order, and the first substrate material layer has a first contact conductor disposed therein. a first contact conductor is disposed in the first substrate material layer. A second wafer including a second die is provided, wherein the second die includes a second substrate material layer, a second interconnect structure, and a second pad, and the second interconnect structure and the second pad are formed on the second substrate material layer in order, and the second substrate material layer has a second contact conductor disposed therein.Type: ApplicationFiled: October 20, 2020Publication date: February 25, 2021Applicant: United Microelectronics Corp.Inventor: Ming-Tse Lin
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Publication number: 20210005559Abstract: A semiconductor package structure and a method for forming the same are disclosed. The semiconductor package structure includes a semiconductor die, a molding layer and an inductor. The semiconductor die includes an active surface, a back surface and a sidewall surface between the active surface and the back surface. The molding layer covers the back surface and the sidewall surface of the semiconductor die. The inductor is in the molding layer. The sidewall surface of the semiconductor die faces toward the inductor.Type: ApplicationFiled: September 17, 2020Publication date: January 7, 2021Inventors: Chun-Hung Chen, Chu-Fu Lin, Ming-Tse Lin
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Patent number: 10886241Abstract: A semiconductor package structure and a method for forming the same are disclosed. The semiconductor package structure includes a semiconductor die, a molding layer and an inductor. The semiconductor die includes an active surface, a back surface and a sidewall surface between the active surface and the back surface. The molding layer covers the back surface and the sidewall surface of the semiconductor die. The inductor is in the molding layer. The sidewall surface of the semiconductor die faces toward the inductor.Type: GrantFiled: September 17, 2020Date of Patent: January 5, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Hung Chen, Chu-Fu Lin, Ming-Tse Lin