Patents by Inventor Ming Tseng
Ming Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250212420Abstract: A semiconductor structure includes a substrate having a memory device region covered by a first dielectric layer, a memory stack structure on the first dielectric layer, an insulating layer conformally covering the memory stack structure and the first dielectric layer, a second dielectric layer on the insulating layer, an etching stop layer on the second dielectric layer, a third dielectric layer on the etching stop layer, and a second interconnecting structure through the third dielectric layer, the etching stop layer and the insulating layer to contact a top surface of the memory stack structure. The insulating layer directly contacts a bottom surface of the etching stop layer and partially covers a bottom surface and a lower sidewall of the second interconnecting structures.Type: ApplicationFiled: March 12, 2025Publication date: June 26, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Jing-Yin Jhang, Chien-Ting Lin
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Publication number: 20250201731Abstract: A semiconductor device includes a first wafer and a second wafer. The first wafer includes a first substrate, a stress tuning structure and a first bonding structure. The stress tuning structure is disposed on the first substrate. The stress tuning structure includes a first oxide layer and a second oxide layer sequentially disposed on the first substrate, and a first refractive index of the first oxide layer is different from a second refractive index of the second oxide layer. The first bonding structure is disposed on the stress tuning structure. The second wafer includes a second substrate and a second bonding structure. The second bonding structure is disposed on the second substrate. The second bonding structure is bonded with the first bonding structure.Type: ApplicationFiled: January 18, 2024Publication date: June 19, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yi-An Shih, Che-Wei Tsai, Da-Jun Lin, I-Ming Tseng, Chung-Sung Chiang, Yu-Chun Chen, Yu-Ping Wang
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Publication number: 20250194436Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.Type: ApplicationFiled: February 24, 2025Publication date: June 12, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
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Publication number: 20250194230Abstract: A semiconductor device includes a first wafer, a second wafer, a dielectric layer and a first metal structure. The first wafer includes a first substrate and a first interconnection layer disposed on the first substrate. The second wafer includes a second substrate and a second interconnection layer. The second substrate includes a buried oxide layer and a semiconductor layer disposed on the buried oxide layer. The second interconnection layer is disposed on the semiconductor layer, in which the second interconnection layer is bonded with the first interconnection layer. The dielectric layer is disposed on the buried oxide layer. The first metal structure is disposed through the dielectric layer, in which an end of the first metal structure physically contacts the buried oxide layer, and the buried oxide layer is grounded through the first metal structure.Type: ApplicationFiled: January 8, 2024Publication date: June 12, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chung-Sung Chiang, Yu-Ping Wang, I-Ming Tseng, Yu-Chun Chen, Yi-An Shih
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Patent number: 12284812Abstract: A semiconductor structure includes a substrate, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and filling the spaces between the memory stack structures, a first interconnecting structure through the second dielectric layer, wherein a top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures, a third dielectric layer on the second dielectric layer, and a plurality of second interconnecting structures through the third dielectric layer, the second dielectric layer and the insulating layer on the top surfaces of the memory stack structures to contact the top surfaces of the memory stack structures.Type: GrantFiled: April 16, 2024Date of Patent: April 22, 2025Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Jing-Yin Jhang, Chien-Ting Lin
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Publication number: 20250107454Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on a first sidewall of the MTJ, and a second spacer on a second sidewall of the MTJ. Preferably, the first spacer and the second spacer are asymmetric, the first spacer and the second spacer have different heights, and a top surface of the MTJ includes a reverse V-shape.Type: ApplicationFiled: December 11, 2024Publication date: March 27, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Ying-Cheng Liu, Yi-An Shih, Yi-Hui Lee, Chen-Yi Weng, Chin-Yang Hsieh, I-Ming Tseng, Jing-Yin Jhang, Yu-Ping Wang
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Patent number: 12262647Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.Type: GrantFiled: March 1, 2024Date of Patent: March 25, 2025Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
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Patent number: 12201032Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on a first sidewall of the MTJ, and a second spacer on a second sidewall of the MTJ. Preferably, the first spacer and the second spacer are asymmetric, the first spacer and the second spacer have different heights, and a top surface of the MTJ includes a reverse V-shape.Type: GrantFiled: April 6, 2021Date of Patent: January 14, 2025Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Ying-Cheng Liu, Yi-An Shih, Yi-Hui Lee, Chen-Yi Weng, Chin-Yang Hsieh, I-Ming Tseng, Jing-Yin Jhang, Yu-Ping Wang
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Publication number: 20240427223Abstract: The focusing module suitable for a lens module includes a focusing ring having a first maximum rotation stroke and being suitable for rotation to adjust the focal length of the lens module. The focusing module connected to the focusing ring includes a bracket, a drive unit disposed on the bracket, a relay gear connected to the drive unit, a first structure formed on the bracket, and a second structure formed on the relay gear. The focusing ring is connected to the relay gear, and the drive unit is configured to drive the relay gear to rotate to drive the focusing ring to rotate. When the relay gear rotates relatively to the bracket, the first structure and the second structure are suitable for stopping each other to limit rotation of the relay gear, so that the relay gear has a second maximum rotation stroke smaller than the first maximum rotation stroke.Type: ApplicationFiled: June 20, 2024Publication date: December 26, 2024Applicant: Coretronic CorporationInventor: Yen-Ming Tseng
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Publication number: 20240387418Abstract: A semiconductor device includes a bottom wafer, a top wafer bonded to the bottom wafer, a first dielectric layer, a second dielectric layer, a deep via conductor structure, and a connection pad. The top wafer includes a first interconnection structure. The first dielectric layer is disposed on the top wafer. The second dielectric layer is disposed on the first dielectric layer. The deep via conductor structure penetrates through the second dielectric layer and the first dielectric layer and is connected with the first interconnection structure. The connection pad is disposed on the second dielectric layer and the deep via conductor structure. A first portion of the second dielectric layer is sandwiched between the connection pad and the first dielectric layer. A second portion of the second dielectric layer is connected with the first portion, and a thickness of the second portion is less than a thickness of the first portion.Type: ApplicationFiled: June 14, 2023Publication date: November 21, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yu-Chun Chen, Yu-Ping Wang, I-Ming Tseng, Yi-An Shih, Chung-Sung Chiang, Chiu-Jung Chiu
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Publication number: 20240371758Abstract: A method for fabricating a semiconductor device includes the steps of first bonding a top wafer to a bottom wafer, in which the top wafer has a first metal interconnection including a first barrier layer exposing from a bottom surface of the top wafer. Next, a dielectric layer is formed on the bottom surface of the top wafer and then a second metal interconnection is formed in the dielectric layer and connected to the first metal interconnection, in which the second metal interconnection includes a second barrier layer and the first barrier layer and the second barrier layer include a H-shape altogether.Type: ApplicationFiled: May 31, 2023Publication date: November 7, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yu-Chun Chen, Yu-Ping Wang, I-Ming Tseng, Yi-An Shih, Chung-Sung Chiang, Chiu-Jung Chiu
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Patent number: 12133474Abstract: A method of fabricating magnetoresistive random access memory, including providing a substrate, forming a bottom electrode layer, a magnetic tunnel junction stack, a top electrode layer and a hard mask layer sequentially on the substrate, wherein a material of the top electrode layer is titanium nitride, a material of the hard mask layer is tantalum or tantalum nitride, and a percentage of nitrogen in the titanium nitride gradually decreases from a top surface of top electrode layer to a bottom surface of top electrode layer, and patterning the bottom electrode layer, the magnetic tunnel junction stack, the top electrode layer and the hard mask layer into multiple magnetoresistive random access memory cells.Type: GrantFiled: September 27, 2023Date of Patent: October 29, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, Jing-Yin Jhang, I-Ming Tseng, Yu-Ping Wang, Chien-Ting Lin, Kun-Chen Ho, Yi-Syun Chou, Chang-Min Li, Yi-Wei Tseng, Yu-Tsung Lai, Jun Xie
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Publication number: 20240357943Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.Type: ApplicationFiled: June 30, 2024Publication date: October 24, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chiu-Jung Chiu, Ya-Sheng Feng, I-Ming Tseng, Yi-An Shih, Yu-Chun Chen, Yi-Hui Lee, Chung-Liang Chu, Hsiu-Hao Hu
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Patent number: 12111501Abstract: The present invention provides a dust-proof device for protecting insertion interfaces arranged in the optical receptacle. The dust-proof device comprises a coupling portion and a flexible arm connected to the coupling portion, wherein the flexible arm may swing or scroll at a location where the coupling portion is connected to the flexible arm. Alternatively, in another embodiment, the present invention further provides an optical receptacle having a plurality of coupling structures respectively having a first insertion interface at a first side and a second insertion interface at a second side, each first insertion interface or second insertion interface may couple to the dust-proof device so as to form an optical connector module for preventing the optical receptacle from being contaminated.Type: GrantFiled: June 13, 2021Date of Patent: October 8, 2024Assignee: ACSUPER TECHNOLOGIES INC.Inventor: Chung-Ming Tseng
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Patent number: 12100028Abstract: Disclosed embodiments describe text-driven AI-assisted short-form video creation. Text from a website is extracted to generate extracted text. Possible summary sentences are formed from the extracted text. The forming is based on natural language processing. The summary sentences are ranked according to an engagement metric. Summary sentences from the possible summary sentences are picked based on a threshold engagement metric value. A list of video scenes is generated based on the summary sentences. Each video scene is associated with a summary sentence. A media asset from a media asset library is chosen for each video scene within the list of video scenes. The choosing is accomplished by machine learning. The list of video scenes, including the media asset that was chosen for each video scene, is compiled into a short-form video. Media is extracted from the website included into the short-form video. The compiling includes a dynamically generated image.Type: GrantFiled: December 5, 2023Date of Patent: September 24, 2024Assignee: Loop Now Technologies, Inc.Inventors: Wu-Hsi Li, Jeremiah Kevin Tu, Hong-Ming Tseng, Xiaochen Zhang
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Patent number: 12096879Abstract: A capsule coffee machine includes a base, a capsule channel formed at a top surface of the base, a gate, an optics lens, a guiding unit, a drip container, a collecting groove, a water injection unit connected with the guiding unit, a driving unit connected with the guiding unit, and an actuator. A bottom of the capsule channel is equipped with the gate. An inside of the capsule channel is equipped with the optics lens. The guiding unit is disposed under the gate and accommodated in the base. The drip container is connected with the guiding unit. The drip container has a mouth, a stopping wall opposite to the mouth, and a peripheral wall extended between the mouth and the stopping wall. The collecting groove is recessed towards a downward direction and in the peripheral wall of the drip container. The actuator is connected with the gate.Type: GrantFiled: June 24, 2021Date of Patent: September 24, 2024Assignee: CHENG UEI PRECISION INDUSTRY CO., LTD.Inventor: Chi-Ming Tseng
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Patent number: 12096172Abstract: A headphone includes an arc-shaped headband, a sliding bar slidably arranged at a tail end of the headband, a hanger pivotally arranged at a tail end of the sliding bar, an earphone unit hanged to the hanger, and a light emitting unit. The earphone unit is fastened to the hanger. The earphone unit includes a housing. A peripheral edge of an outer surface of the housing protrudes outward to form a protruding ring. The light emitting unit is fastened to the housing. The light emitting unit includes a light guiding module and a light emitter. The light guiding module includes a light guider and a light blocker. An inner end of the light blocker is provided with a contacting portion which is closely cooperated with the protruding ring, and an inner end of the light guider closely abuts against the protruding ring.Type: GrantFiled: September 2, 2022Date of Patent: September 17, 2024Assignee: CHENG UEI PRECISION INDUSTRY CO., LTD.Inventors: Chi-Ming Tseng, Chin-Chung Lin
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Publication number: 20240290024Abstract: Disclosed embodiments provide techniques for dynamic synthetic video chat agent replacement. A human host receives a request for a video chat initiated by a user. An image for a synthetic host including a representation of an individual is retrieved. The image of the synthetic host is selected based on information about the user. Aspects of the individual included in the image are extracted using one or more processors. A video performance by the human host responding to the statement or query by the user is captured. A synthetic host performance is created in which the video performance of the human host is dynamically replaced by the individual that was extracted so that the synthetic host performance responds to the user statement or query. The synthetic host performance is rendered to the user and supplemented with additional synthetic host performances as the video chat continues.Type: ApplicationFiled: February 23, 2024Publication date: August 29, 2024Applicant: Loop Now Technologies, Inc.Inventors: Wu-Hsi Li, Edwin Chiu, Jerry Ting Kwan Luk, Hong-Ming Tseng, Jeremiah Kevin Tu
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Publication number: 20240292069Abstract: Disclosed embodiments provide techniques for synthesized realistic metahuman short-form videos. A photorealistic representation of an individual is accessed from media sources including videos, photographs, livestreams, or a 360-degree recording of a human host. The individual can be selected based on information on the viewer of the short-form video, such as purchase history, viewing history, and metadata. The photorealistic representation is isolated using machine learning and is used to create a three-dimensional (3D) model of the individual, based on a game engine. A realistic synthetic performance is created by combining the 3D model of the individual with animation generated by a game engine. The synthesized performance can include the voice of the human host. The synthesized performance is inserted into a metaverse environment and rendered to a viewer as a short-form video, including an ecommerce window with an on-screen product card and virtual purchase cart.Type: ApplicationFiled: February 23, 2024Publication date: August 29, 2024Applicant: Loop Now Technologies, Inc.Inventors: Hong-Ming Tseng, Edwin Chiu, Wu-Hsi Li, Jeremiah Kevin Tu
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Publication number: 20240292070Abstract: Disclosed embodiments provide techniques for iterative AI prompt optimization for video generation. A first text template to be read by a large language model (LLM) neural network is accessed. The template includes control parameters that are populated from within a website. The populated template is submitted as a request to the LLM neural network, which generates a first video script. The first video script is used to create a first short-form video. The first short-form video is evaluated based on one or more performance metrics. The text template, short-form video, website information, and evaluation are used to train a machine learning model that is used to create a second text template. The second text template can be used to generate a second short-form video. The evaluation of iterative text templates and resulting short-form videos continues until a usable video is produced.Type: ApplicationFiled: April 10, 2024Publication date: August 29, 2024Applicant: Loop Now Technologies, Inc.Inventors: Wu-Hsi Li, Edwin Chiu, Hong-Ming Tseng, Xiaochen Zhang