Abstract: Smart rings and methods of manufacturing smart rings are provided. A waterproof design and method of manufacturing of a smart ring, in accordance with one implementation, includes a band having at least an outer surface and an inner surface. The inner surface of the band includes features configured to support electronic components. The waterproofing design and method of manufacturing includes a laser etching a portion of the inner surface and subsequent to the laser etching of the portion, applying an epoxy over the electronic components and over the laser etched portion of the inner surface. Prior to the laser etching, forming an edge rib on the portion of the inner surface, wherein the laser etching is subsequently on the edge rib. Furthermore, the laser etched portion includes an increased contact area for bonding with the epoxy for the waterproof design.

Abstract: A semiconductor structure includes a substrate, at least one dielectric layer and a capacitor structure. The at least one dielectric layer is disposed over the substrate, and the at least one dielectric layer includes a step edge profile. The capacitor structure is disposed over the substrate. The capacitor structure includes a bottom electrode, a capacitor dielectric layer and a top electrode. The bottom electrode covers the step edge profile of the at least one dielectric layer and has a first step profile substantially conformal to the step edge profile of the at least one dielectric layer. The capacitor dielectric layer covers the bottom electrode and has a second step profile substantially conformal to the first step profile. The top electrode covers the capacitor dielectric layer.

Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.

Abstract: A testing fixture for a cell temperature probe includes a microcomputer, a temperature probe, a measurement case, a temperature instrument and heaters. The microcomputer configured to receive a control command for executing a testing process. The measurement case has an outer surface and an inner surface. The outer surface includes a probe-contacting area used for being contacted by the cell temperature probe within a formation device in the testing process. The temperature instrument is electrically connected to the microcomputer and has a sensing terminal disposed on the inner surface of the measurement case. The location of the sensing terminal is aligned with the probe-contacting area in a direction of a thickness of the measurement case. The heaters are electrically connected to the microcomputer and thermally to the measurement case.

Abstract: A testing fixture for a cell temperature probe includes a microcomputer, a temperature probe, a measurement case, a temperature instrument and heaters. The microcomputer configured to receive a control command for executing a testing process. The measurement case has an outer surface and an inner surface. The outer surface includes a probe-contacting area used for being contacted by the cell temperature probe within a formation device in the testing process. The temperature instrument is electrically connected to the microcomputer and has a sensing terminal disposed on the inner surface of the measurement case. The location of the sensing terminal is aligned with the probe-contacting area in a direction of a thickness of the measurement case. The heaters are electrically connected to the microcomputer and thermally to the measurement case.

Abstract: A complex mechanical seal for vertical multiple stage pump includes a hollow cylinder fixed plate positioned in the vertical multiple stage pump. It is coupled to a fixed barrel. The bottom hole of fixed barrel is used as the passage of pump axle. A long axle bushing in the inner part of the fixed plate is fixed on the pump axle. A balance plate is positioned below long axle bushing. The circumference of balance plate has a flange. The mechanical seal is fixed on the upper space of the balance plate and fixed on long axle bushing. A return water passage is connected to the upper part of balance plate and to inlet of pump, and the high pressure region. A and low pressure region B, are needed as the pushing force. The complex structure of balance plate and mechanical seal is simultaneously easier and quicker to assemble and disassemble.

Abstract: Complex mechanical seal for vertical multiple stage pump comprises: a hollow cylinder fixed plate positioned in the final stage of outlet gate in the vertical multiple stage pump, it is coupled with an inner wall surface of fixed barrel to form a sealed face, the bottom hole of fixed barrel is used the passage of pump axle; a long axle bushing in the inner part of the fixed plate is fixed on the pump axle; a balance plate is positioned below long axle bushing and combined with said long axle bushing becoming one part of it, the circumference of balance plate has a promotion flange to divide with the inner wall surface to form a gap; the mechanical seal is fixed on the upper place of the balance plate and fixed on long axle bushing; and a return water passage which communicated with the upper part of balance plate and connected to inlet of pump, thus within the fixed plate, the high pressure region A and low pressure region B formed at the lower part and upper part respectively are need as the pushing force of

Abstract: A method for fabricating a STI structure includes a pad oxide layer and a hard masking layer first formed over a semiconductor substrate. A trench is formed in the substrate. A first insulating layer is formed over the substrate. The surface of the first insulating layer within the trench is be between the hard masking layer surface and the semiconductor substrate surface. An insulating cap layer is formed over the first insulating layer with a hardness at least about as large as the hard masking layer. A second insulating layer is formed over the insulating cap layer. A chemical mechanical polishing (CMP) process is performed, using the hard masking layer as a polishing stop, to planarize over the substrate. A process of dipping the substrate into a HF acid solution is performed to remove the hard masking layer and the pad oxide layer, in which the process also simultaneously removes the remaining second insulating layer and the remaining insulating cap layer.

Abstract: A method for etching metal which can increase the metal-to-photoresist etching selectivity of a metal layer aimed to be etched with respect to a photoresist layer overlaying the metal layer. The method includes a first step of forming a cap oxide layer over the metal layer; a second step of forming a photoresist layer with a desired pattern over the cap oxide layer; a third step of conducting an ion implantation process on the photoresist layer; and a final step of conducting an etching process on the semiconductor wafer by using the photoresist layer as a mask so as to etch away exposed portions of the metal layer that are uncovered by the photoresist layer. Through experiments, it is found that the invention provides a significantly improved etching selectivity over the prior art.

Abstract: A buried contact structure formed on a semiconductor substrate. A single polysilicon layer is formed on a field oxide layer. The polysilicon layer is patterned and etched to form an interconnect layer. A silicide layer is formed on the sidewall of the interconnect layer. The silicide layer connects a buried contact region with the interconnect layer to make electrical contact between the interconnect layer and a source/drain region.

Abstract: A process for coding and code marking a read-only memory device makes use of a buffer layer, such as silicon nitrides (Si.sub.3 N.sub.4) or silicon oxynitrides (SiN.sub.x O.sub.y), to form a code mark therein. Owing to the etching selectivity between the buffer layer and an underlying layer, for example, silicon oxides, the programmed region not covered by the word lines will not suffer from etching damage while forming the code mark. Therefore, the coding and code marking process can employ the same mask layer, but without the need for two different photomasking procedures to implement code programming and identification code marking.

Abstract: A new method of planarizing an integrated circuit is achieved. The dielectric layers between the conductive layers of an integrated circuit are formed and planarized via A first silicon oxide layer is deposited over the metal layer. This is covered with a spin-on-glass layer. This layer is dried by baking. The spin-on-glass layer is now fully cured. The cured spin-on-glass layer is now ion implanted under the conditions of between about 1E15 to 1E17 atoms/cm.sup.2 and energy between about 50 to 100 KeV. A silicon oxide layer is deposited thereover. Via openings are now made through the silicon oxide layers and the spin-on-glass layer and filled with metal. This results in excellent planarity with no poisoned via problems. Most importantly, this method can be used for submicron technologies having conductor lines which are spaced from one another by submicron feature size and can be processed without the use of an etch-back process for the cured spin on and glass layer.

Abstract: In the fabrication of VLSI circuits, the diffusion barrier layer on the pad areas are removed prior to the formation of metal layer. Metal layer on the pad areas are thus directly contact with the underlying SiO.sub.2 layer, thereby improving the pad bonding yield.