Patents by Inventor Ming-Tung Chang
Ming-Tung Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240088279Abstract: A method for forming a semiconductor structure includes the steps of forming a stacked structure on a substrate, forming an insulating layer on the stacked structure, forming a passivation layer on the insulating layer, performing an etching process to form an opening through the passivation layer and the insulating layer to expose a portion of the stacked structure and an extending portion of the insulating layer, and forming a contact structure filling the opening and directly contacting the stacked structure, wherein the extending portion of the insulating layer is adjacent to a surface of the stacked structure directly contacting the contact structure.Type: ApplicationFiled: November 27, 2023Publication date: March 14, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ming-Hua Chang, Po-Wen Su, Chih-Tung Yeh
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Patent number: 11916131Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.Type: GrantFiled: November 4, 2020Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: De-Fang Chen, Teng-Chun Tsai, Cheng-Tung Lin, Li-Ting Wang, Chun-Hung Lee, Ming-Ching Chang, Huan-Just Lin
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Patent number: 10776558Abstract: A testing method includes the following operations: performing a place and route procedure according to a netlist file corresponding to a chip to generate first layout data; determining whether to replace a flip-flop circuit in the chip with a gated flip-flop circuit according to the first layout data to generate second layout data; and running a test on the chip according to the second layout data.Type: GrantFiled: March 21, 2019Date of Patent: September 15, 2020Assignee: Global Unichip (Nanjing) Ltd.Inventors: Shih-Hsin Chen, Te-Hsun Fu, Ming-Tung Chang
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Publication number: 20200151299Abstract: A testing method includes the following operations: performing a place and route procedure according to a netlist file corresponding to a chip, in order to generate first layout data; determining whether to replace a flip-flop circuit in the chip with a gated flip-flop circuit according to the first layout data, in order to generate second layout data; and running a test on the chip according to the second layout data.Type: ApplicationFiled: March 21, 2019Publication date: May 14, 2020Inventors: Shih-Hsin Chen, Te-Hsun Fu, Ming-Tung Chang
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Patent number: 8487645Abstract: A through-silicon via (TSV) testing structure is disclosed herein and includes a plurality of controllers, a plurality of transmitters and a plurality of receivers. The controllers are configured to output a first controlling signal and a second controlling signal. The transmitters are respectively connected to the output end of the through-silicon via and one of the controllers, and output a testing output signal in accordance with the first controlling signal and the second controlling signal. The receivers are respectively connected to the input end of the through-silicon via and another one of the controllers, and input a testing input signal in accordance with the first controlling signal and the second controlling signal.Type: GrantFiled: February 23, 2011Date of Patent: July 16, 2013Assignee: Global Unichip CorporationInventors: Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng
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Patent number: 8468407Abstract: In a method for creating a clock domain in a layout of an integrated circuit, a test circuit of the integrated circuit includes a plurality of first scan cells and a plurality of second scan cells, the first scan cells are arranged to be on a first scan chain, and the second scan cells are arranged to be on a second scan chain. The method includes: for a first region in the layout, determining whether the first region needs a test clock domain adjustment according to densities of first scan cells and second scan cells within the first region; and when it is determined that the first region needs the test clock domain adjustment, arranging at least one first scan cell within the first region to be on the second scan chain.Type: GrantFiled: August 19, 2011Date of Patent: June 18, 2013Assignees: Global Unichip Corp., National Taiwan University, Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng, Jen-Yang Wen, Chien-Mo Li
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Publication number: 20120233513Abstract: In a method for creating a clock domain in a layout of an integrated circuit, a test circuit of the integrated circuit includes a plurality of first scan cells and a plurality of second scan cells, the first scan cells are arranged to be on a first scan chain, and the second scan cells are arranged to be on a second scan chain. The method includes: for a first region in the layout, determining whether the first region needs a test clock domain adjustment according to densities of first scan cells and second scan cells within the first region; and when it is determined that the first region needs the test clock domain adjustment, arranging at least one first scan cell within the first region to be on the second scan chain.Type: ApplicationFiled: August 19, 2011Publication date: September 13, 2012Inventors: Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng, Jen-Yang Wen, Chien-Mo Li
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Publication number: 20120012841Abstract: A through-silicon via (TSV) testing structure is disclosed herein and includes a plurality of controllers, a plurality of transmitters and a plurality of receivers. The controllers are configured to output a first controlling signal and a second controlling signal. The transmitters are respectively connected to the output end of the through-silicon via and one of the controllers, and output a testing output signal in accordance with the first controlling signal and the second controlling signal. The receivers are respectively connected to the input end of the through-silicon via and another one of the controllers, and input a testing input signal in accordance with the first controlling signal and the second controlling signal.Type: ApplicationFiled: February 23, 2011Publication date: January 19, 2012Applicant: Global Unichip CorporationInventors: Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng
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Publication number: 20090188681Abstract: A fire extinguisher includes a container having a chamber for receiving a dry chemical agent, a cover attached to the container and having a passage for allowing the dry chemical agent to flow out of the cover, and an agitating device received in the container for agitating the dry chemical agent and for preventing the dry extinguishing agent from being hardened. A rod is rotatably received in the container and extended out of the container and includes an agitator, and a hand wheel is secured to the rod for rotating the rod and the agitator relative to the container. A carrier is rotatably attached to a seat for supporting the container and for adjustably securing the container to the seat at selected angular positions.Type: ApplicationFiled: January 30, 2008Publication date: July 30, 2009Inventor: Ming Tung Chang
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Patent number: 7512851Abstract: A method and apparatus time-division demultiplexes and decompresses a compressed input stimulus provided at a selected data rate R1, into a decompressed stimulus, driven at a selected data rate R2, for driving selected scan chains in a scan-based integrated circuit using a plurality of time-division demultiplexors and time-division multiplexors for shifting stimuli and test responses in and out of high-speed I/O pads in order to reduce test time, test cost, and scan pin count. A synthesis method is also proposed for synthesizing the time-division multiplexors, decompressors, compressors, and time-division multiplexors.Type: GrantFiled: July 29, 2004Date of Patent: March 31, 2009Assignee: Syntest Technologies, Inc.Inventors: Laung-Terng Wang, Khader S. Abdel-Hafez, Xiaoqing Wen, Boryau (Jack) Sheu, Fei-Sheng Hsu, Augusli Kifli, Shyh-Horng Lin, Shianling Wu, Shun-Miin (Sam) Wang, Ming-Tung Chang
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Publication number: 20090037786Abstract: A method and apparatus for testing or diagnosing faults in a scan-based integrated circuit using a unified self-test and scan-test technique. The method and apparatus comprises using a unified test controller to ease prototype debug and production test. The unified test controller further comprises using a capture clock generator and a plurality of domain clock generators each embedded in a clock domain to perform self-test or scan-test. The capture clocks generated by the capture clock generator are used to guide at-speed or reduced-speed self-test (or scan-test) within each clock domain. The frequency of these capture clocks can be totally unrelated to those of system clocks controlling the clock domains. This unified approach allows designers to test or diagnose stuck-type and non-stuck-type faults with a low-cost DFT (design-for-test) tester or a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus.Type: ApplicationFiled: September 30, 2008Publication date: February 5, 2009Inventors: Laung-Terng Wang, Xiaoqing Wen, Khader S. Abdel-Hafez, Shyh-Horng Lin, Hsin-Po Wang, Ming-Tung Chang, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Chi-Chan Hsu
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Patent number: 7444567Abstract: A method and apparatus for testing or diagnosing faults in a scan-based integrated circuit using a unified self-test and scan-test technique. The method and apparatus comprises using a unified test controller to ease prototype debug and production test. The unified test controller further comprises using a capture clock generator and a plurality of domain clock generators each embedded in a clock domain to perform self-test or scan-test. The capture clocks generated by the capture clock generator are used to guide at-speed or reduced-speed self-test (or scan-test) within each clock domain. The frequency of these capture clocks can be totally unrelated to those of system clocks controlling the clock domains. This unified approach allows designers to test or diagnose stuck-type and non-stuck-type faults with a low-cost DFT (design-for-test) tester or a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus.Type: GrantFiled: April 4, 2003Date of Patent: October 28, 2008Assignee: Syntest Technologies, Inc.Inventors: Laung-Terng (L.-T.) Wang, Xiaoqing Wen, Khader S. Abdel-Hafez, Shyh-Horng Lin, Hsin-Po Wang, Ming-Tung Chang, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Chi-Chan Hsu
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Patent number: 7284175Abstract: A method and apparatus for inserting design-for-debug (DFD) circuitries in an integrated circuit to debug or diagnose DFT modules, including scan cores, memory BIST (built-in self-test) cores, logic BIST cores, and functional cores. The invention further comprises using a DFD controller for executing a plurality of DFD commands to debug or diagnosis the DFT modules embedded with the DFD circuitries. When used alone or combined together, these DFD commands will detect or locate physical failures in the DFT modules in the integrated circuit on an evaluation board or system using a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to synthesize the DFD controller and DFD circuitries according to the IEEE 1149.1 Boundary-scan Std. The DFD controller supports, but is not limited to, the following DFD commands: RUN_SCAN, RUN_MBIST, RUN_LBIST, DBG_SCAN, DBG_MBIST, DBG_LBIST, DBG_FUNCTION, SELECT, SHIFT, SHIFT_CHAIN, CAPTURE, RESET, BREAK, RUN, STEP, and STOP.Type: GrantFiled: November 22, 2006Date of Patent: October 16, 2007Assignee: Syntest Technologies, Inc.Inventors: Laung-Terng Wang, Ming-Tung Chang, Hao-Jan Chao, Xiaoqing Wen, Po-Ching Hsu
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Publication number: 20070168803Abstract: A method and apparatus for inserting design-for-debug (DFD) circuitries in an integrated circuit to debug or diagnose DFT modules, including scan cores, memory BIST (built-in self-test) cores, logic BIST cores, and functional cores. The invention further comprises using a DFD controller for executing a plurality of DFD commands to debug or diagnosis the DFT modules embedded with the DFD circuitries. When used alone or combined together, these DFD commands will detect or locate physical failures in the DFT modules in the integrated circuit on an evaluation board or system using a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to synthesize the DFD controller and DFD circuitries according to the IEEE 1149.1 Boundary-scan Std. The DFD controller supports, but is not limited to, the following DFD commands: RUN_SCAN, RUN_MBIST, RUN_LBIST, DBG_SCAN, DBG_MBIST, DBG_LBIST, DBG_FUNCTION, SELECT, SHIFT, SHIFT_CHAIN, CAPTURE, RESET, BREAK, RUN, STEP, and STOP.Type: ApplicationFiled: November 22, 2006Publication date: July 19, 2007Inventors: Laung-Terng Wang, Ming-Tung Chang, Hao-Jan Chao, Xiaoqing Wen, Po-Ching Hsu
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Patent number: 7191373Abstract: A method and apparatus for inserting design-for-debug (DFD) circuitries in an integrated circuit to debug or diagnose DFT modules, including scan cores, memory BIST (built-in self-test) cores, logic BIST cores, and functional cores. The invention further comprises using a DFD controller for executing a plurality of DFD commands to debug or diagnosis the DFT modules embedded with the DFD circuitries. When used alone or combined together, these DFD commands will detect or locate physical failures in the DFT modules in the integrated circuit on an evaluation board or system using a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to synthesize the DFD controller and DFD circuitries according to the IEEE 1149.1 Boundary-scan Std. The DFD controller supports, but is not limited to, the following DFD commands: RUN_SCAN, RUN_MBIST, RUN_LBIST, DBG_SCAN, DBG_MBIST, DBG_LBIST, DBG_FUNCTION, SELECT, SHIFT, SHIFT_CHAIN, CAPTURE, RESET, BREAK, RUN, STEP, and STOP.Type: GrantFiled: February 27, 2002Date of Patent: March 13, 2007Assignee: Syntest Technologies, Inc.Inventors: Laung-Terng (L.-T.) Wang, Ming-Tung Chang, Shyh-Horng Lin, Hao-Jan Chao, Jaehee Lee, Hsin-Po Wang, Xiaoqing Wen, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Sen-Wei Tsai, Chi-Chan Hsu
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Publication number: 20050055617Abstract: A method and apparatus for time-division demultiplexing and decompressing a compressed input stimulus 421, provided at a selected data-rate R1 421, into a decompressed stimulus 424, 426, 433, 435, driven at a selected data-rate R2 442, for driving selected scan chains in a scan-based integrated circuit 401. The scan-based integrated circuit 401 contains a high-speed clock CK1 443, a low-speed clock CK2 442, and a plurality of scan chains 411, . . . , 418, each scan chain comprising multiple scan cells coupled in series. The method and apparatus comprises using a plurality of time-division demultiplexors (TDDMs) 402, 403 and time-division multiplexors (TDMs) 408, 409 for shifting stimuli 421 and test responses 444 in and out of high-speed I/O pads. When applied to the scan-based integrated circuit 401 embedded with one or more pairs of decompressors 404, 405 and compressors 406, 407, it can further reduce the circuit's test time, test cost, and scan pin count.Type: ApplicationFiled: July 29, 2004Publication date: March 10, 2005Inventors: Laung-Terng Wang, Khader Abdel-Hafez, Xiaoqing Wen, Boryau Sheu, Fei-Sheng Hsu, Augusli Kifli, Shyh-Horng Lin, Shianling Wu, Shun-Miin Wang, Ming-Tung Chang
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Publication number: 20040268181Abstract: A method and apparatus for testing or diagnosing faults in a scan-based integrated circuit using a unified self-test and scan-test technique. The method and apparatus comprises using a unified test controller to ease prototype debug and production test. The unified test controller further comprises using a capture clock generator and a plurality of domain clock generators each embedded in a clock domain to perform self-test or scan-test. The capture clocks generated by the capture clock generator are used to guide at-speed or reduced-speed self-test (or scan-test) within each clock domain. The frequency of these capture clocks can be totally unrelated to those of system clocks controlling the clock domains. This unified approach allows designers to test or diagnose stuck-type and non-stuck-type faults with a low-cost DFT (design-for-test) tester or a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus.Type: ApplicationFiled: April 4, 2003Publication date: December 30, 2004Inventors: Laung-Terng Wang, Xiaoqing Wen, Khader S. Abdel-Hafez, Shyh-Horng Lin, Hsin-Po Wang, Ming-Tung Chang, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Chi-Chan Hsu
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Publication number: 20020138801Abstract: A method and apparatus for inserting design-for-debug (DFD) circuitries in an integrated circuit to debug or diagnose DFT modules, including scan cores, memory BIST (built-in self-test) cores, logic BIST cores, and functional cores. The invention further comprises using a DFD controller for executing a plurality of DFD commands to debug or diagnosis the DFT modules embedded with the DFD circuitries. When used alone or combined together, these DFD commands will detect or locate physical failures in the DFT modules in the integrated circuit on an evaluation board or system using a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to synthesize the DFD controller and DFD circuitries according to the IEEE 1149.1 Boundary-scan Std. The DFD controller supports, but is not limited to, the following DFD commands: RUN_SCAN, RUN_MBIST, RUN_LBIST, DBG_SCAN, DBG_MBIST, DBG_LBIST, DBG_FUNCTION, SELECT, SHIFT, SHIFT_CHAIN, CAPTURE, RESET, BREAK, RUN, STEP, and STOP.Type: ApplicationFiled: February 27, 2002Publication date: September 26, 2002Inventors: Laung-Terng Wang, Ming-Tung Chang, Shyh-Horng Lin, Hao-Jan Chao, Jaehee Lee, Hsin-Po Wang, Xiaoqing Wen, Po-Ching Hsu, Shih-Chia Kao, Meng-Chyi Lin, Sen-Wei Tsai, Chi-Chan Hsu