Abstract: A method for regenerating a secondary battery is disclosed and includes a discharge step before drilling, wherein the secondary battery is discharged so that no current is generated between two electrodes; a drilling step, wherein the secondary battery is drilled from an electrode terminal towards an internal direction of the secondary battery until passing through a spacer inside the secondary battery to form a drilled hole in the spacer; a solution replenishing step, wherein a solution injection needle is used to pass through the drilled hole to inject internally to the secondary battery with a supplemental electrolyte solution and the injection pressure of the supplemental electrolyte solution injected is greater than the internal pressure inside the secondary battery; and a sealing step, wherein the solution injection needle is withdrawn from the drilled hole and a sealant is applied to the drilled hole until the sealant is cured and solidified.

Abstract: A lithium ion secondary battery includes a battery casing, an electrode set reeled inside the battery casing and having a positive electrode and a negative electrode, a positive electrode terminal exposed from a top end of the battery casing and connected to the positive electrode and a negative electrode terminal located at a bottom end of the battery casing and connected to the negative electrode, the lithium ion secondary battery further includes: a super capacitor substrate, disposed in the battery casing and extended between two distal ends of the battery casing, and includes a substrate, a first copper foil connected to the positive electrode terminal, a second copper foil connected to the negative electrode terminal, and at least one capacitor connected to the first copper foil and the second copper foil; and an electrolyte, suitable to be applied in the lithium ion secondary battery.

Abstract: A semiconductor device has a lower metal layer, a lower dielectric layer on top of the lower metal layer, an upper metal layer on top of the lower dielectric layer, an upper dielectric layer on top of the upper metal layer, and a contact region formed as a cavity that extends through the upper dielectric layer, the upper metal layer and the lower dielectric layer for access to a solder pad portion of the lower metal layer. A dielectric lining layer lines a peripheral cavity-confining surface of the cavity, and is transverse to a plane of the lower metal layer. The dielectric lining layer isolates the upper metal layer from the lower metal layer while permitting access to the solder pad portion of the lower metal layer. An electrical contact fills the cavity, and enables external electrical connection with the lower metal layer.

Abstract: A semiconductor chip module includes a chip-mounting member having opposite first and second surfaces, a set of circuit traces, and a plurality of plated through holes that extend through the first and second surfaces and that are connected to the circuit traces. A dielectric tape member bonds adhesively a semiconductor chip on the chip-mounting member. A first conductor unit connects electrically contact pads on a pad mounting surface of the semiconductor chip and the circuit traces. A plurality of solder balls are disposed on one of the first and second surfaces of the chip-mounting member, are aligned with and are connected to the plated through holes in the chip-mounting member, respectively.

Abstract: A semiconductor chip module includes a chip-mounting member having opposite first and second surfaces, a set of circuit traces, and a plurality of plated through holes that extend through the first and second surfaces and that are connected to the circuit traces. A dielectric tape member bonds adhesively a semiconductor chip on the chip-mounting member. A first conductor unit connects electrically contact pads on a pad mounting surface of the semiconductor chip and the circuit traces. A plurality of solder balls are disposed on one of the first and second surfaces of the chip-mounting member, are aligned with and are connected to the plated through holes in the chip-mounting member, respectively.

Abstract: A semiconductor chip module includes first and second semiconductor chips, and a dielectric tape layer. The first semiconductor chip has a pad mounting surface with a plurality of first bonding pads provided thereon. The dielectric tape layer has opposite first and second adhesive surfaces. The first adhesive surface is adhered onto the pad mounting surface of the first semiconductor chip. The dielectric tape layer is formed with a plurality of holes at positions registered with the first bonding pads to expose the first bonding pads. Each of the holes is confined by a wall that cooperates with a registered one of the first bonding pads to form a contact receiving space. A plurality of conductive contacts are placed in the contact receiving spaces, respectively. The second semiconductor chip has a chip mounting surface adhered onto the second adhesive surface of the dielectric tape layer.

Abstract: A semiconductor device has a lower metal layer, a lower dielectric layer on top of the lower metal layer, an upper metal layer on top of the lower dielectric layer, an upper dielectric layer on top of the upper metal layer, and a contact region formed as a cavity that extends through the upper dielectric layer, the upper metal layer and the lower dielectric layer for access to a solder pad portion of the lower metal layer. A dielectric lining layer lines a peripheral cavity-confining surface of the cavity, and is transverse to a plane of the lower metal layer. The dielectric lining layer isolates the upper metal layer from the lower metal layer while permitting access to the solder pad portion of the lower metal layer. An electrical contact fills the cavity, and enables external electrical connection with the lower metal layer.

Abstract: A multi-chip semiconductor module includes first and second substrates. The first substrate has opposite first and second surfaces, a plurality of first conductive vias that extend through the first and second surfaces, and a first circuit layout patterned on the second surface and connected electrically to the first conductive vias. The second substrate has opposite first and second surfaces, a plurality of second conductive vias that extend through the first and second surfaces of the second substrate, a second circuit layout patterned on the second surface of the second substrate and connected electrically to the second conductive vias, and a chip-receiving opening formed therein. The first surface of the second substrate is bonded on the second surface of the first substrate such that the second circuit layout is connected electrically to the first circuit layout through the first and second conductive vias.

Abstract: A method for manufacturing a semiconductor device includes the steps of forming a first conductive bump on a substrate, forming a second conductive bump on a semiconductor chip, forming a plurality of spaced apart dielectric supporting pads on one of the substrate and the semiconductor chip, mounting the semiconductor chip on the substrate to confine therebetween a gap, bonding together the first and second conductive bumps, and forming an insulating layer that fills in the gap and that encapsulates the supporting pads and the first and second conductive bumps.

Abstract: An integrated circuit chip including a circuit board unit and a plurality of contact pads on a top surface of the unit. A die having a plurality of solder pads is positioned adjacent the circuit board unit with the solder pads wire-bonded to the contact pads. A lead frame having connecting leads is positioned on the circuit board unit with the leads connected to the solder pads via a conductive contact layer. A plastic layer encapsulates the circuit board unit and at least a portion with the lead frame.

Abstract: A semiconductor device has a lower metal layer, a lower dielectric layer on top of the lower metal layer, an upper metal layer on top of the lower dielectric layer, an upper dielectric layer on top of the upper metal layer, and a contact region formed as a cavity that extends through the upper dielectric layer, the upper metal layer and the lower dielectric layer for access to a solder pad portion of the lower metal layer. A dielectric lining layer lines a peripheral cavity-confining surface of the cavity, and is transverse to a plane of the lower metal layer. The dielectric lining layer isolates the upper metal layer from the lower metal layer while permitting access to the solder pad portion of the lower metal layer. An electrical contact fills the cavity, and enables external electrical connection with the lower metal layer.

Abstract: A method for manufacturing a semiconductor device includes the steps of forming a hardened photoresist layer on a bonding pad of a semiconductor chip, forming a conductive layer on the hardened photoresist layer to form a conductive bump on the bonding pad, forming a plurality of supporting pads on the semiconductor chip, attaching a chip-mounting substrate on the semiconductor chip such that the supporting pads interconnect the semiconductor chip and the substrate, and forming an insulating layer that fills a space between the semiconductor chip and the substrate and that encloses the conductive bump.

Abstract: A method for manufacturing a semiconductor device includes the steps of forming a first conductive bump on a substrate, forming a second conductive bump on a semiconductor chip, forming a plurality of spaced apart dielectric supporting pads on one of the substrate and the semiconductor chip, mounting the semiconductor chip on the substrate to confine therebetween a gap, bonding together the first and second conductive bumps, and forming an insulating layer that fills in the gap and that encapsulates the supporting pads and the first and second conductive bumps.

Abstract: A method for manufacturing a semiconductor device includes the steps of forming a first conductive bump on a substrate, forming a second conductive bump on a semiconductor chip, forming a plurality of spaced apart dielectric supporting pads on one of the substrate and the semiconductor chip, mounting the semiconductor chip on the substrate to confine therebetween a gap, bonding together the first and second conductive bumps, and forming an insulating layer that fills in the gap and that encapsulates the supporting pads and the first and second conductive bumps.

Abstract: A method for manufacturing a semiconductor device includes the steps of forming a hardened photoresist layer on a bonding pad of a semiconductor chip, forming a conductive layer on the hardened photoresist layer to form a conductive bump on the bonding pad, forming a plurality of supporting pads on the semiconductor chip, attaching a chip-mounting substrate on the semiconductor chip such that the supporting pads interconnect the semiconductor chip and the substrate, and forming an insulating layer that fills a space between the semiconductor chip and the substrate and that encloses the conductive bump.

Abstract: In a method of fabricating an integrated circuit chip, a circuit board unit is formed with a bore, a plurality of contact pads, and a plurality of positioning notches that correspond to the contact pads. A die is attached to a bottom surface of the circuit board unit, and solder pads on the die are wire-bonded to the contact pads using conductive wires that extend through the bore. Leads of a lead frame are inserted respectively into the positioning notches and are bonded to the contact pads. A plastic protective layer is then formed to encapsulate the circuit board unit and at least a portion of the lead frame.

Abstract: A testing base for a semiconductor device includes a retaining seat, a base board and a press unit. The retaining seat has a top side formed with a receiving cavity. The receiving cavity is adapted to receive the semiconductor device therein. The base board is mounted in a bottom portion of the receiving cavity of the retaining seat. The base board has a contacting side that confronts a contact mounting side of the semiconductor device when the semiconductor device is received in the receiving cavity. The contacting side is provided with a plurality of conductive contact pads adapted to connect electrically and respectively with contact members on the contact mounting side of the semiconductor device. The base board further has a plurality of contact terminals that extend outwardly through the retaining seat and that are connected electrically to the contact pads.

Abstract: A method for fabricating an integrated circuit chip includes the steps of: (a) forming a circuit board unit with a die-receiving cavity, and a plurality of contact pads on a top surface of the circuit board unit; (b) forming a die having an upper surface provided with a plurality of solder pads; (c) placing the die in the die-receiving cavity such that the solder pads on the die are exposed; (d) wire-bonding the solder pads to the contact pads via conductive wires; (e) placing a lead frame on the circuit board unit, and connecting leads on the lead frame to corresponding ones of the contact pads via a conductive contact layer; and (f) forming a plastic protective layer to encapsulate the circuit board unit and at least a portion of the lead frame.

Abstract: A method for fabricating an integrated circuit chip includes the steps of: (a) forming a circuit board unit with a die-receiving cavity, and a plurality of contact pads on a top surface of the circuit board unit; (b) forming a die having an upper surface provided with a plurality of solder pads; (c) placing the die in the die-receiving cavity such that the solder pads on the die are exposed; (d) wire-bonding the solder pads to the contact pads via conductive wires; (e) placing a lead frame on the circuit board unit, and connecting leads on the lead frame to corresponding ones of the contact pads via a conductive contact layer; and (f) forming a plastic protective layer to encapsulate the circuit board unit and at least a portion of the lead frame.

Abstract: A method for manufacturing a semiconductor device includes the steps of forming a first conductive bump on a substrate, forming a second conductive bump on a semiconductor chip, forming a plurality of spaced apart dielectric supporting pads on one of the substrate and the semiconductor chip, mounting the semiconductor chip on the substrate to confine therebetween a gap, bonding together the first and second conductive bumps, and forming an insulating layer that fills in the gap and that encapsulates the supporting pads and the first and second conductive bumps.