Abstract: A process for depositing a layer of uniform thickness on an uneven surface of a substrate is disclosed. The layer could be deposited by plasma or chemical vapor deposition (CVD). The uneven surface of the substrate has horizontal surfaces and vertical sidewalls and is located on a movable platform. The platform is tilted and rotated as the layer is deposited so that the ions or the flow of chemical vapor reaches the horizontal surface and the sidewall at a similar incident angle. Thereby, the layer is evenly deposited and has a uniform thickness with proper coverage and planarization.

Abstract: A process for depositing a layer of uniform thickness on an uneven surface of a substrate is disclosed. The layer could be deposited by plasma or chemical vapor deposition (CVD). The uneven surface of the substrate has horizontal surfaces and vertical sidewalls and is located on a movable platform. The platform is tilted and rotated as the layer is deposited so that the ions or the flow of chemical vapor reaches the horizontal surface and the sidewall at a similar incident angle. Thereby, the layer is evenly deposited and has a uniform thickness with proper coverage and planarization.

Abstract: A method of fabricating an EPROM cell by forming a trench in a semiconductor substrate, forming a first insulating layer over the surface of the substrate, and the sidewalls and bottom of the trench, forming individual polycrystalline silicon layers on the sidewalls of the trench, implanting a dopant into the substrate in the bottom of, and regions adjacent, the trench, forming a second insulating layer over the polycrystalline silicon layers, forming a control gate over the polycrystalline silicon layers and an electrical contact to the bottom of the trench.

Abstract: A method, and resultant structure, for manufacturing ROM (Read Only Memory) integrated circuits that may be coded, or programmed, after metallization, is described. A plurality of parallel bit lines is formed in a semiconductor substrate. There is a thin insulating layer over the substrate. A plurality of parallel word lines is formed over the thin insulating layer, arranged orthogonally to the bit lines. Gate electrodes of a single conductive material are in coded regions under the word lines, over the thin insulating layer, and between the bit lines, where a ROM code etch has been performed, such that there is a gap between the single conductive material and the word lines. The ROM code etch is performed by an RCA etch of titanium or titanium nitride previously formed between the single conductive material and the word lines. Gate electrodes of two layers of conductive material are in uncoded regions connected to and under the word lines, over the thin insulating layer, and between the bit lines.

Abstract: A new method of forming the dielectric layer of an integrated circuit is described. A thick insulating layer is formed over semiconductor device structures in and on a semiconductor substrate. A first metal layer is deposited over the thick insulating layer. The first metal layer is etched using conventional photolithography and etching techniques to form the desired metal pattern on the surface of the thick insulating layer. The intermetal dielectric layer is formed by first covering the patterned first metal layer with a layer of silicon oxide. The silicon oxide layer is covered with a layer of spin-on-glass material which is baked and cured. A second layer of silicon oxide completes the intermetal dielectric layer. Via openings are formed through the intermetal dielectric layer to the underlying patterned first metal layer.