Patents by Inventor Ming-Wei Chang

Ming-Wei Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240146091
    Abstract: A vehicle power management system and a power management method thereof are provided. The power management method includes: determining, by a microcontroller, whether or not a voltage of an ignition-off signal is less than a voltage threshold when the microcontroller receives the ignition-off signal; stopping a vehicle power supply from charging a backup battery, and using the vehicle power supply to charge a back-end load; activating a counter of the microcontroller; stopping the vehicle power supply from charging the back-end load, and using the backup battery to charge the back-end load when a counting time of the counter reaches a first time threshold; sending, by the microcontroller, the ignition-off signal to the back-end load when the counting time of the counter reaches a second time threshold; and stopping the backup battery from charging the back-end load when the counting time of the counter reaches a third time threshold.
    Type: Application
    Filed: April 17, 2023
    Publication date: May 2, 2024
    Inventors: MING-ZONG WU, CHUN-KAI CHANG, LI-WEI CHENG
  • Publication number: 20240145632
    Abstract: A micro light emitting device includes an epitaxial structure, a conductive layer, and a first insulating layer. The epitaxial structure has a first surface and a second surface opposite to the first surface, and includes a first semiconductor layer, an active layer and a second semiconductor layer that are arranged in such order in a direction from the first surface to the second surface. The conductive layer is formed on a surface of the first semiconductor layer away from the active layer. The first insulating layer is formed on the surface of the first semiconductor layer away from the active layer, and exposes at least a part of the conductive layer.
    Type: Application
    Filed: October 23, 2023
    Publication date: May 2, 2024
    Inventors: Ming-Chun TSENG, Shaohua HUANG, Hongwei WANG, Kang-Wei PENG, Su-Hui LIN, Xiaomeng LI, Chi-Ming TSAI, Chung-Ying CHANG
  • Patent number: 11971601
    Abstract: An imaging lens assembly includes a plurality of optical elements and an accommodating assembly, wherein the accommodating assembly is for containing the optical elements. The accommodating assembly includes a conical-shaped light blocking sheet and a lens barrel. The conical-shaped light blocking sheet includes an out-side portion and a conical portion, and the conical portion is connected to the out-side portion. The conical portion includes a conical structure tapered from the out-side portion toward one of an object-side and an image-side along the optical axis. The lens barrel is disposed on one side of the conical portion. The optical elements include a most object-side optical element, a most image-side optical element and at least one optical element. The conical structure of the conical-shaped light blocking sheet is physically contacted with only one of the lens barrel, the most object-side optical element and the most image-side optical element.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: April 30, 2024
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Yu-Chen Lai, Chih-Wei Cheng, Ming-Ta Chou, Ming-Shun Chang
  • Publication number: 20240136226
    Abstract: An ammonium fluoride gas may be used to form a protection layer for one or more interlayer dielectric layers, one or more insulating caps, and/or one or more source/drain regions of a semiconductor device during a pre-clean etch process. The protection layer can be formed through an oversupply of nitrogen trifluoride during the pre-clean etch process. The oversupply of nitrogen trifluoride causes an increased formation of ammonium fluoride, which coats the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) with a thick protection layer. The protection layer protects the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) during the pre-clean process from being etched by fluorine ions formed during the pre-clean process.
    Type: Application
    Filed: January 2, 2024
    Publication date: April 25, 2024
    Inventors: Li-Wei CHU, Ying-Chi SU, Yu-Kai CHEN, Wei-Yip LOH, Hung-Hsu CHEN, Chih-Wei CHANG, Ming-Hsing TSAI
  • Publication number: 20240131538
    Abstract: An annular airflow regulating apparatus includes a cup-shaped element and an adjustment element. The cup-shaped element has a bowl and a bottom, integrated to form a first chamber. The bottom has a tapered channel parallel to an axis and penetrating through the bottom. A ring-shaped groove is disposed between the tapered channel and the bottom. The ring-shaped groove has an annular plane perpendicular to the axis. The adjustment element, having a tapered portion and second holes, is movably disposed in the cup-shaped element. The tapered portion protrudes into the tapered channel A tapered annular gap is formed between the tapered portion and the tapered channel. When the adjustment element is moved with respect to the cup-shaped element, a width of the tapered annular gap is varied, and thereupon a flow rate and velocity of the process gas would be varied accordingly.
    Type: Application
    Filed: December 8, 2022
    Publication date: April 25, 2024
    Inventors: CHEN-CHUNG DU, Ming-Jyh Chang, Chang-Yi Chen, Ming-Hau Tsai, Ko-Chieh chao, Yi-Wei Lin
  • Publication number: 20240135187
    Abstract: Provided are computing systems, methods, and platforms that train query processing models, such as large language models, to perform query intent classification tasks by using retrieval augmentation and multi-stage distillation. Unlabeled training examples of queries may be obtained, and a set of the training examples may be augmented with additional feature annotations to generate augmented training examples. A first query processing model may annotate the retrieval augmented queries to generate inferred labels for the augmented training examples. A second query processing model may be trained on the inferred labels, distilling the query processing model that was trained with retrieval augmentation into a non-retrieval augmented query processing model. The second query processing model may annotate the entire set of unlabeled training examples. Another stage of distillation may train a third query processing model using the entire set of unlabeled training examples without retrieval augmentation.
    Type: Application
    Filed: October 22, 2023
    Publication date: April 25, 2024
    Inventors: Krishna Pragash Srinivasan, Michael Bendersky, Anupam Samanta, Lingrui Liao, Luca Bertelli, Ming-Wei Chang, Iftekhar Naim, Siddhartha Brahma, Siamak Shakeri, Hongkun Yu, John Nham, Karthik Raman, Raphael Dominik Hoffmann
  • Publication number: 20240136420
    Abstract: A thin film transistor includes a substrate, a semiconductor layer, a gate insulating layer, a gate, a source and a drain. The semiconductor layer is located above the substrate. The gate insulating layer is located above the semiconductor layer. The gate is located above the gate insulating layer and overlapping with the semiconductor layer. The gate includes a first portion, a second portion and a third portion. The first portion is extending along the surface of the gate insulating layer and directly in contact with the gate insulating layer. The second portion is separated from the gate insulating layer. Taking the surface of the gate insulating layer as a reference, the top surface of the second portion is higher than the top surface of the first portion. The third portion connects the first portion to the second portion. The source and the drain are electrically connected to the semiconductor layer.
    Type: Application
    Filed: December 1, 2022
    Publication date: April 25, 2024
    Applicant: AUO Corporation
    Inventors: Kuo-Jui Chang, Wen-Tai Chen, Chi-Sheng Chiang, Yu-Chuan Liao, Chien-Sen Weng, Ming-Wei Sun
  • Publication number: 20240126327
    Abstract: The present disclosure provides an electronic wearable device. The electronic wearable device includes a first module having a first contact and a second module having a second contact. The first contact is configured to keep electrical connection with the second contact in moving with respect to each other during a wearing period.
    Type: Application
    Filed: October 14, 2022
    Publication date: April 18, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chao Wei LIU, Wei-Hao CHANG, Yung-I YEH, Jen-Chieh KAO, Tun-Ching PI, Ming-Hung CHEN, Hui-Ping JIAN, Shang-Lin WU
  • Patent number: 11961919
    Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate, where a top portion of the fin comprises a layer stack that includes alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin; forming openings in the fin on opposing sides of the dummy gate structure; forming source/drain regions in the openings; removing the dummy gate structure to expose the first semiconductor material and the second semiconductor material under the dummy gate structure; performing a first etching process to selectively remove the exposed first semiconductor material, where after the first etching process, the exposed second semiconductor material form nanostructures, where each of the nanostructures has a first shape; and after the first etching process, performing a second etching process to reshape each of the nanostructures into a second shape different from the first shape.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chung Chang, Hsiu-Hao Tsao, Ming-Jhe Sie, Shun-Hui Yang, Chen-Huang Huang, An Chyi Wei, Ryan Chia-Jen Chen
  • Publication number: 20240113032
    Abstract: Interconnect structure packages (e.g., through silicon vias (TSV) packages, through interlayer via (TIV) packages) may be pre-manufactured as opposed to forming TIVs directly on a carrier substrate during a manufacturing process for a semiconductor die package at backend packaging facility. The interconnect structure packages may be placed onto a carrier substrate during manufacturing of a semiconductor device package, and a semiconductor die package may be placed on the carrier substrate adjacent to the interconnect structure packages. A molding compound layer may be formed around and in between the interconnect structure packages and the semiconductor die package.
    Type: Application
    Filed: April 25, 2023
    Publication date: April 4, 2024
    Inventors: Kai-Fung CHANG, Chin-Wei LIANG, Sheng-Feng WENG, Ming-Yu YEN, Cheyu LIU, Hung-Chih CHEN, Yi-Yang LEI, Ching-Hua HSIEH
  • Publication number: 20240113112
    Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Inventors: Ryan Chia-Jen Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen
  • Patent number: 11929314
    Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hsien Huang, Peng-Fu Hsu, Yu-Syuan Cai, Min-Hsiu Hung, Chen-Yuan Kao, Ken-Yu Chang, Chun-I Tsai, Chia-Han Lai, Chih-Wei Chang, Ming-Hsing Tsai
  • Publication number: 20240071776
    Abstract: A chip packaging structure and a method for fabricating the same are provided. The chip package structure includes a conductive substrate, a dam and a metal shielding layer. The conductive substrate includes a substrate, vias and electrodes. The substrate has first and second board surfaces opposite to each other. The vias penetrate through the first board surface and the second board surface, and a part of the vias is disposed in a first die-bonding region on which a chip is to be arranged. The electrodes extend from the first board surface to the second board surface through the vias. The dam is formed on the first board surface to surround the first die-bonding region, and the dam has a height higher than that of the chip. The metal shielding layer covers the dam and a part of the first board surface that do not overlap with the electrodes.
    Type: Application
    Filed: December 2, 2022
    Publication date: February 29, 2024
    Inventors: DEI-CHENG LIU, CHIA-SHUAI CHANG, MING-YEN PAN, JIAN-YU SHIH, JHIH-WEI LAI, SHIH-HAN WU
  • Patent number: 11915976
    Abstract: An ammonium fluoride gas may be used to form a protection layer for one or more interlayer dielectric layers, one or more insulating caps, and/or one or more source/drain regions of a semiconductor device during a pre-clean etch process. The protection layer can be formed through an oversupply of nitrogen trifluoride during the pre-clean etch process. The oversupply of nitrogen trifluoride causes an increased formation of ammonium fluoride, which coats the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) with a thick protection layer. The protection layer protects the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) during the pre-clean process from being etched by fluorine ions formed during the pre-clean process.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Wei Chu, Ying-Chi Su, Yu-Kai Chen, Wei-Yip Loh, Hung-Hsu Chen, Chih-Wei Chang, Ming-Hsing Tsai
  • Publication number: 20220409531
    Abstract: A pharmaceutical delivery device, comprising a cylindrical body formed from a plurality of concentrically arranged layers, each layer being formed from a biodegradable material and incorporating at least one active pharmaceutical agent. Optionally, the device comprises an outer layer, and inner layer and one or more intermediate layers, wherein at least one of the one or more intermediate layers is formed from a material having a greater rate of degradation that the inner and outer layers such that the inner and outer layers separate in use.
    Type: Application
    Filed: September 24, 2020
    Publication date: December 29, 2022
    Inventors: Ming-Wei Chang, James McLaughlin
  • Patent number: 11003865
    Abstract: Systems and methods for pre-training and fine-tuning of neural-network-based language models are disclosed in which a neural-network-based textual knowledge retriever is trained along with the language model. In some examples, the knowledge retriever obtains documents from an unlabeled pre-training corpus, generates its own training tasks, and learns to retrieve documents relevant to those tasks. In some examples, the knowledge retriever is further refined using supervised open-QA questions. The framework of the present technology provides models that can intelligently retrieve helpful information from a large unlabeled corpus, rather than requiring all potentially relevant information to be stored implicitly in the parameters of the neural network. This framework may thus reduce the storage space and complexity of the neural network, and also enable the model to more effectively handle new tasks that may be different than those on which it was pre-trained.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: May 11, 2021
    Assignee: GOOGLE LLC
    Inventors: Kenton Chiu Tsun Lee, Kelvin Gu, Zora Tung, Panupong Pasupat, Ming-Wei Chang
  • Patent number: 10828263
    Abstract: A layered body comprising: a core region; at least one intermediate layer disposed around the core region; and an outer layer disposed around the at least one intermediate layer, wherein at least one of the at least one intermediate layers comprises a gas, the layered body having at least one dimension, measured across the body and through the core region, of 100 ?m or less.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: November 10, 2020
    Assignee: UCL Business Ltd
    Inventors: Mohan Edirisinghe, Ming Wei Chang, Eleanor Stride
  • Patent number: 10780059
    Abstract: A layered body comprising: a core region; at least one intermediate layer disposed around the core region; and an outer layer disposed around the at least one intermediate layer, wherein at least one of the at least one intermediate layers comprises a gas, the layered body having at least one dimension, measured across the body and through the core region, of 100 ?m or less.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: September 22, 2020
    Assignee: UCL Business Ltd
    Inventors: Mohan Edirisinghe, Ming Wei Chang, Eleanor Stride
  • Publication number: 20180104192
    Abstract: A layered body comprising: a core region; at least one intermediate layer disposed around the core region; and an outer layer disposed around the at least one intermediate layer, wherein at least one of the at least one intermediate layers comprises a gas, the layered body having at least one dimension, measured across the body and through the core region, of 100 ?m or less.
    Type: Application
    Filed: December 6, 2017
    Publication date: April 19, 2018
    Applicant: UCL Business PLC
    Inventors: Mohan Edirisinghe, Ming Wei Chang, Eleanor Stride
  • Publication number: 20180092860
    Abstract: A layered body comprising: a core region; at least one intermediate layer disposed around the core region; and an outer layer disposed around the at least one intermediate layer, wherein at least one of the at least one intermediate layers comprises a gas, the layered body having at least one dimension, measured across the body and through the core region, of 100 ?m or less.
    Type: Application
    Filed: December 6, 2017
    Publication date: April 5, 2018
    Applicant: UCL Business PLC
    Inventors: Mohan Edirisinghe, Ming Wei Chang, Eleanor Stride