Patents by Inventor Ming-Wei Cheng
Ming-Wei Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12009256Abstract: A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.Type: GrantFiled: June 20, 2023Date of Patent: June 11, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming-Da Cheng, Wen-Hsiung Lu, Chin Wei Kang, Yung-Han Chuang, Lung-Kai Mao, Yung-Sheng Lin
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Patent number: 12009345Abstract: An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.Type: GrantFiled: January 3, 2023Date of Patent: June 11, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Meng-Tse Chen, Chung-Shi Liu, Chih-Wei Lin, Hui-Min Huang, Hsuan-Ting Kuo, Ming-Da Cheng
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Patent number: 12009322Abstract: A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer.Type: GrantFiled: February 13, 2022Date of Patent: June 11, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Hsuan Tai, Ting-Ting Kuo, Yu-Chih Huang, Chih-Wei Lin, Hsiu-Jen Lin, Chih-Hua Chen, Ming-Da Cheng, Ching-Hua Hsieh, Hao-Yi Tsai, Chung-Shi Liu
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Publication number: 20240168266Abstract: An optical path folding element includes an optical portion, a connection portion, matte structures and a light blocking layer. The optical portion has an optical surface and two reflective surfaces. A light beam enters into the optical path folding element via the optical surface and is reflected inside the optical path folding element through the optical surface. Each reflective surface is configured to reflect the light beam again inside the optical path folding element. The connection portion has connection surfaces connected to the optical surface and the reflective surfaces. The matte structures are at least disposed on and integrally formed with the connection portion. Each unitary structure of the matte structures is tapered off and recessed from the connection portion, such that the outer surface of the connection portion has an undulating shape. The light blocking layer is at least disposed on the connection portion for blocking light.Type: ApplicationFiled: October 3, 2023Publication date: May 23, 2024Applicant: LARGAN PRECISION CO., LTD.Inventors: Chen Wei FAN, Syuan Ruei LAI, Jyun-Jia CHENG, Ming-Ta CHOU
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Publication number: 20240172347Abstract: A lighting device includes a driver, a first light string, a second light string, a constant current controller and a pulse width modulation controller. The driver is configured to provide a DC driving current to a shunt node. The first light string is electrically coupled between the shunt node and a ground terminal, and the first light string is driven by a first pulsating direct current. The second light string and the constant current controller are electrically coupled in series between the shunt node and the ground terminal. The pulse width modulation controller is configured to provide a pulse signal to the constant current controller, and the constant current controller controls a pulse frequency of a second pulsating direct current supplied for the second light string according to the pulse signal.Type: ApplicationFiled: November 16, 2023Publication date: May 23, 2024Inventors: Chih-Hsien Wang, Kuan-Hsien Tu, Kai-Wei Chen, Ming-Chieh Cheng
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Publication number: 20240162038Abstract: A photomask structure including a first layout pattern and a second layout pattern is provided. The second layout pattern is located on one side of the first layout pattern. The first layout pattern and the second layout pattern are separated from each other. The first layout pattern has a first edge and a second edge opposite to each other. The second layout pattern has a third edge and a fourth edge opposite to each other. The third edge of the second layout pattern is adjacent to the first edge of the first layout pattern. The second layout pattern includes a first extension portion exceeding an end of the first layout pattern. The first extension portion includes a first protruding portion protruding from the third edge of the second layout pattern. The first protruding portion exceeds the first edge of the first layout pattern.Type: ApplicationFiled: February 10, 2023Publication date: May 16, 2024Applicant: United Microelectronics Corp.Inventors: Chien Heng Liu, Chia-Wei Huang, Yung-Feng Cheng, Ming-Jui Chen
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Publication number: 20240153896Abstract: A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die.Type: ApplicationFiled: January 12, 2024Publication date: May 9, 2024Inventors: Hui-Min Huang, Chih-Wei Lin, Tsai-Tsung Tsai, Ming-Da Cheng, Chung-Shi Liu, Chen-Hua Yu
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Publication number: 20240146091Abstract: A vehicle power management system and a power management method thereof are provided. The power management method includes: determining, by a microcontroller, whether or not a voltage of an ignition-off signal is less than a voltage threshold when the microcontroller receives the ignition-off signal; stopping a vehicle power supply from charging a backup battery, and using the vehicle power supply to charge a back-end load; activating a counter of the microcontroller; stopping the vehicle power supply from charging the back-end load, and using the backup battery to charge the back-end load when a counting time of the counter reaches a first time threshold; sending, by the microcontroller, the ignition-off signal to the back-end load when the counting time of the counter reaches a second time threshold; and stopping the backup battery from charging the back-end load when the counting time of the counter reaches a third time threshold.Type: ApplicationFiled: April 17, 2023Publication date: May 2, 2024Inventors: MING-ZONG WU, CHUN-KAI CHANG, LI-WEI CHENG
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Publication number: 20240147286Abstract: Apparatus and methods are provided for UE-assisted tethering report. In one novel aspect, UE-assisted tethering report is generated with UE-assisted procedure based on latency measurement configuration. In one embodiment, the UE-assisted tethering report includes one or more elements comprising one bit to inform the activation of tethering mode, latency of packet transmission, and other side-information related to tethering path. In one embodiment, the UE-assisted procedure is inserting a measurement timestamp or recording timing of a predefined transport block (TB) of the packet. In another novel aspect, the UE performs a jitter measurement for an extended reality (XR) traffic, sends a UE-assisted information report for an end-to-end path of the XR traffic based on the jitter measurements, wherein the UE-assisted information includes one or more elements comprising jitter information and burst arrival time.Type: ApplicationFiled: October 23, 2023Publication date: May 2, 2024Inventors: JING-WEI CHEN, Tao Chen, Yih-Shen Chen, Ming-Yuan Cheng
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Patent number: 11971601Abstract: An imaging lens assembly includes a plurality of optical elements and an accommodating assembly, wherein the accommodating assembly is for containing the optical elements. The accommodating assembly includes a conical-shaped light blocking sheet and a lens barrel. The conical-shaped light blocking sheet includes an out-side portion and a conical portion, and the conical portion is connected to the out-side portion. The conical portion includes a conical structure tapered from the out-side portion toward one of an object-side and an image-side along the optical axis. The lens barrel is disposed on one side of the conical portion. The optical elements include a most object-side optical element, a most image-side optical element and at least one optical element. The conical structure of the conical-shaped light blocking sheet is physically contacted with only one of the lens barrel, the most object-side optical element and the most image-side optical element.Type: GrantFiled: June 18, 2021Date of Patent: April 30, 2024Assignee: LARGAN PRECISION CO., LTD.Inventors: Yu-Chen Lai, Chih-Wei Cheng, Ming-Ta Chou, Ming-Shun Chang
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Publication number: 20240125713Abstract: A method includes directing light at a first side of a semiconductor structure; detecting a first light intensity at a second side of the semiconductor structure, wherein the first light intensity corresponds to the light that penetrated the semiconductor structure from the first side to the second side; and comparing the first light intensity to a second light intensity, wherein the second light intensity corresponds to an expected intensity of light.Type: ApplicationFiled: January 10, 2023Publication date: April 18, 2024Inventors: Hao Chun Yang, Ming-Da Cheng, Pei-Wei Lee, Mirng-Ji Lii
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Patent number: 11961791Abstract: A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A conductive region is disposed in the polymer region and electrically coupled to the redistribution line. The conductive region includes a second flat top surface not higher than the first flat top surface.Type: GrantFiled: May 18, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Wen Hsiao, Ming-Da Cheng, Chih-Wei Lin, Chen-Shien Chen, Chih-Hua Chen, Chen-Cheng Kuo
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Patent number: 11961944Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate, active devices and transparent conductive patterns. The active devices are formed on the semiconductor substrate. The transparent conductive patterns are formed over the active devices and electrically connected to the active devices. The transparent conductive patterns are made of a metal oxide material. The metal oxide material has a first crystalline phase with a prefer growth plane rich in oxygen vacancy, and has a second crystalline phase with a prefer growth plane poor in oxygen vacancy.Type: GrantFiled: January 31, 2023Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-En Yen, Ming-Da Cheng, Mirng-Ji Lii, Wen-Hsiung Lu, Cheng-Jen Lin, Chin-Wei Kang, Chang-Jung Hsueh
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Patent number: 11936418Abstract: A radar signal processing system with a self-interference cancelling function includes an analog front end (AFE) processor, an analog to digital converter (ADC), an adaptive interference canceller (AIC), and a digital to analog converter (DAC). The AFE processor receives an original input signal and generates an analog input signal. The ADC converts the analog input signal to a digital input signal. The AIC generates a digital interference signal digital interference signal by performing an adaptive interference cancellation process according to the digital input signal. The DAC converts the digital interference signal to an analog interference signal. Finally, the analog interference signal is fed back to the AFE and cancelled from the original input signal in the AFE processor while performing the front end process, reducing the interference of the static interference from the leaking of a close-by transmitter during the front end process.Type: GrantFiled: April 27, 2021Date of Patent: March 19, 2024Assignee: KAIKUTEK INC.Inventors: Mike Chun-Hung Wang, Chun-Hsuan Kuo, Mohammad Athar Khalil, Wen-Sheng Cheng, Chen-Lun Lin, Chin-Wei Kuo, Ming Wei Kung, Khoi Duc Le
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Publication number: 20240083742Abstract: A micro electro mechanical system (MEMS) includes a circuit substrate comprising electronic circuitry, a support substrate having a recess, a bonding layer disposed between the circuit substrate and the support substrate, through holes passing through the circuit substrate to the recess, a first conductive layer disposed on a front side of the circuit substrate, and a second conductive layer disposed on an inner wall of the recess. The first conductive layer extends into the through holes and the second conductive layer extends into the through holes and coupled to the first conductive layer.Type: ApplicationFiled: November 15, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ting-Li YANG, Kai-Di WU, Ming-Da CHENG, Wen-Hsiung LU, Cheng Jen LIN, Chin Wei KANG
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Patent number: D590339Type: GrantFiled: June 25, 2008Date of Patent: April 14, 2009Assignee: System General CorporationInventors: Ta-Yung Yang, Shih-Jen Yang, Hung-Sen Tu, Ming-Wei Cheng