Abstract: An optical member driving mechanism for connecting an optical member is provided, including a fixed portion and a first adhesive member. The fixed portion includes a first member and a second member, wherein the first member is fixedly connected to the second member via the first adhesive member.

Abstract: A bridge module is provided. The bridge module comprise a first transmission unit electrically connected to a host to receive a power status signal from the host; a second transmission unit electrically connected to a data transceiver device to have data transmission with the data transceiver device at a download data transmission speed; and a processing device electrically connected to the first transmission unit and the second transmission unit, and configured to adjust the download data transmission speed and a processor clock of the processing device according to the power status signal. An operation method is also provided.

Abstract: A bridge module is provided. The bridge module comprise a first transmission unit electrically connected to a host to receive a power status signal from the host; a second transmission unit electrically connected to a data transceiver device to have data transmission with the data transceiver device at a download data transmission speed; and a processing device electrically connected to the first transmission unit and the second transmission unit, and configured to adjust the download data transmission speed and a processor clock of the processing device according to the power status signal. An operation method is also provided.

Abstract: An output buffer with an offset cancellation structure for an LCD source driver includes an operational amplifier, for driving an output signal of the output buffer according to a data signal from a data input terminal of the output buffer; a reference voltage generator, for generating a reference voltage and inputting the reference voltage to the operational amplifier; and a sampling capacitor, coupled between a second input terminal of the operational amplifier and the data input terminal of the output buffer in a first phase, and coupled between the second input terminal of the operational amplifier and an output terminal of the operational amplifier in a second phase, wherein the second input terminal of the operational amplifier is further coupled to the output terminal of the operational amplifier in the first phase. The output signal outputs the data signal where the offset voltage is cancelled in the second phase.

Abstract: An output buffer with an offset cancellation structure for an LCD source driver includes an operational amplifier, for driving an output signal of the output buffer according to a data signal from a data input terminal of the output buffer; a reference voltage generator, for generating a reference voltage and inputting the reference voltage to the operational amplifier; and a sampling capacitor, coupled between a second input terminal of the operational amplifier and the data input terminal of the output buffer in a first phase, and coupled between the second input terminal of the operational amplifier and an output terminal of the operational amplifier in a second phase, wherein the second input terminal of the operational amplifier is further coupled to the output terminal of the operational amplifier in the first phase. The output signal outputs the data signal where the offset voltage is cancelled in the second phase.

Abstract: A system-on-chip (SoC) and a booting method thereof are disclosed. The SoC is coupled to an external memory and includes a read only memory (ROM) and a processor. The ROM stores a first firmware image. The processor is coupled to the ROM. The processor reads the first firmware image from the ROM and verifies the state of the first firmware image. If the first firmware image is damaged, the processor reads a second firmware image from the external memory and verifies whether the second firmware image is legal. If the verification of the second firmware image succeeds, the processor reads and executes the second firmware image to perform a booting process.

Abstract: A training method for language learning is provided, which includes: building user data of a user in a storage unit; retrieving target contents from a CTC database to a UTC database of the storage unit in accordance with difficulty levels of the target contents and the acquired level; setting a test by selecting test contents of the target contents in the UTC database as questions of the test; scoring the user's answers to the questions; performing an AL adjustment for the acquired level in accordance with a score of the test; performing a DL adjustment for the difficulty levels in accordance with correctness of each answer to the respective question in the test; and uploading the target contents with changed difficulty levels to the CTC database to update the target contents in the CTC database.

Abstract: The message reporting system has a receiver module, a processing module, a message type setting module, and at least one sending module. The receiver module receives an SOS message from at least one victim and the SOS message contains contact information of a bully. The processing module is connected to the receiver module and produces a reporting message in accordance with the SOS message, and then sets the bully in the contact information of the bully as a receiver of the reporting message. The message type setting module is connected to the processing module and is used for setting a type of the reporting message. The at least one sending module is connected to the processing module and is used for sending the reporting message to the bully.

Abstract: A system-on-chip (SoC) and a booting method thereof are disclosed. The SoC is coupled to an external memory and includes a read only memory (ROM) and a processor. The ROM stores a first firmware image. The processor is coupled to the ROM. The processor reads the first firmware image from the ROM and verifies the state of the first firmware image. If the first firmware image is damaged, the processor reads a second firmware image from the external memory and verifies whether the second firmware image is legal. If the verification of the second firmware image succeeds, the processor reads and executes the second firmware image to perform a booting process.

Abstract: A computer system with a non-support hyper-transport processor and a controlling method of a hyper-transport bus thereof. The computer system includes a system management controller, a Northbridge, a hyper-transport bus, a central processing unit and a power management signal line. The Northbridge is electrically connected to the system management controller through the hyper-transport bus. The central processing unit is electrically connected to the Northbridge, and the central processing unit does not support the hyper-transport bus. The system management controller outputs a power management signal to the central processing unit and the Northbridge through the power management signal line so that the hyper-transport bus changes from a first working frequency to a second working frequency, and from a first bus width to a second bus width.

Abstract: A core logic device of a computer system includes a programmable interrupt controller (PIC), an input/output advanced programmable interrupt controller (I/O APIC) and a virtual wire unit. The PIC outputs a control signal to the virtual wire unit via an interrupt pin in response to an external interrupt signal asserted by a peripheral device before an operating system is loaded in the computer system. The virtual wire unit outputs an interrupt control packet to the CPU in response to the control signal wherein the interrupt vector contents carried by the interrupt control packet are ignored by the CPU. After the operating system is loaded in the computer system, the I/O APIC outputs another interrupt control packet to the CPU in response to the external interrupt signal.

Abstract: A computer system and a power management method thereof are provided. The computer system includes a system management controller, a northbridge, a hyper transport bus, a central processing unit and a power management signal line. The northbridge is electrically connected to the system management controller via the hyper transport bus. The central processing unit is electrically connected to the northbridge but does not support the hyper transport bus. The system management controller outputs a power management signal to the central processing unit and the northbridge via the power management signal line. When the system management controller asserts the power management signal, data transmission is stopped with the disconnection of the hyper transport bus, and the central processing unit changes to a power-saving state from a working state.

Abstract: A computer system with a non-support hyper-transport processor and a controlling method of a hyper-transport bus thereof. The computer system includes a system management controller, a Northbridge, a hyper-transport bus, a central processing unit and a power management signal line. The Northbridge is electrically connected to the system management controller through the hyper-transport bus. The central processing unit is electrically connected to the Northbridge, and the central processing unit does not support the hyper-transport bus. The system management controller outputs a power management signal to the central processing unit and the Northbridge through the power management signal line so that the hyper-transport bus changes from a first working frequency to a second working frequency, and from a first bus width to a second bus width.

Abstract: A computer system and a power management method thereof are provided. The computer system includes system management controller, a northbridge, a hyper transport bus, a central processing unit and a power management signal line. The northbridge is electrically connected to the system management controller via the hyper transport bus. The central processing unit is electrically connected to the northbridge but does not support the hyper transport bus. The system management controller outputs a power management signal to the central processing unit and the northbridge via the power management signal line. When the system management controller asserts the power management signal, data transmission is stopped with the disconnection of the hyper transport bus, and the central processing unit changes to a power-saving state from a working state.

Abstract: A computer system with power management and the method thereof. First, the CPU outputs a power management signal to the south bridge. The south bridge responds with a stop clock signal, and then the CPU responds with a stop grant message. The north bridge receives and analyzes the stop grant message to identify a power supply mode. If the power supply mode is to suspend the main power supplied from the power supply, the north bridge outputs a state transition signal to the peripheral, which then responds with an acknowledge signal. The north bridge passes the stop grant message to the south bridge after receiving the acknowledge signal. The south bridge receives the stop grant message and outputs a power control signal accordingly. The power supply receives the power control signal for suspending the corresponding power accordingly.

Abstract: A computer system has a processor, a basic input and output system (BIOS), a plurality of configurable hardware components, configuration data and an operating system (OS). The method includes executing the plurality of code segments from a starting point of the BIOS for initializing the plurality of hardware components, preparing to receive a configuration request, setting a program interrupt point, switching the computer into a user configuration mode for configuration request, continuing to execute the code segments by the program interrupt point, and loading the operating system.

Abstract: A core logic device is provided to a computer system having a central processing unit (CPU) and a peripheral device. The core logic device includes a programmable interrupt controller (PIC), an input/output advanced programmable interrupt controller (I/O APIC) and a virtual wire unit. The PIC outputs a control signal to the virtual wire unit via an interrupt pin in response to an external interrupt signal asserted by the peripheral device before an operating system is loaded in the computer system. Accordingly, the virtual wire unit outputs an interrupt control packet to the CPU wherein the interrupt vector contents carried by the interrupt control packet is ignored by the CPU. Alternatively, after the operating system is loaded in the computer system, the I/O APIC outputs another interrupt control packet to the CPU in response to the external interrupt signal.

Abstract: A method for verifying optimization of processor link. First, an initial bus width and an initial bus frequency of a bus coupled between a CPU and a Northbridge are set, such that the bus operates at the initial bus width and the initial bus frequency. Next, a read request for a Southbridge is generated. Next, a bus disconnection signal is output by the Southbridge to disconnect the CPU and the Northbridge when the Southbridge receives the read request. A timer is initialized for calculating an elapsed time value and an optimization verification signal at a first voltage level is generated. Next, a bus connection signal is output by the Southbridge when the elapsed time value reaches a predetermined value. Next, the voltage level of the optimization verification signal is transformed to a second voltage level. Finally, the CPU and the Northbridge are reconnected by the bus according to the bus connection signal, such that the bus operates at another bus operating bus width and another bus operating frequency.

Abstract: A method for CPU power management and bus optimization. First, the bus operates at an initial bus bandwidth and an initial bus frequency first. Next, power management settings of the CPU, the Northbridge and the Southbridge are initialized, such that the CPU operates at a CPU operating frequency with a CPU operating voltage. Next, a CPU operating frequency and voltage adjustment is output to the Southbridge. Next, a bus disconnection signal is output by the Southbridge to disconnect the CPU and the Northbridge, and a timer for calculating an elapsed time value is initialized. Next, the CPU operating frequency and the CPU operating voltage are adjusted according to the CPU operating frequency and voltage adjustment. Next, a bus connection signal is output by the Southbridge when the elapsed time value reaches a predetermined value. Next, the CPU and the Northbridge are reconnected by the bus according to the bus connection signal.

Abstract: A method for verifying optimization of processor link. First, an initial bus width and an initial bus frequency of a bus coupled between a CPU and a Northbridge are set, such that the bus operates at the initial bus width and the initial bus frequency. Next, a read request for a Southbridge is generated. Next, a bus disconnection signal is output by the Southbridge to disconnect the CPU and the Northbridge when the Southbridge receives the read request. A timer is initialized for calculating an elapsed time value and an optimization verification signal at a first voltage level is generated. Next, a bus connection signal is output by the Southbridge when the elapsed time value reaches a predetermined value. Next, the voltage level of the optimization verification signal is transformed to a second voltage level. Finally, the CPU and the Northbridge are reconnected by the bus according to the bus connection signal, such that the bus operates at another bus operating bus width and another bus operating frequency.