Abstract: A radar signal processing system with a self-interference cancelling function includes an analog front end (AFE) processor, an analog to digital converter (ADC), an adaptive interference canceller (AIC), and a digital to analog converter (DAC). The AFE processor receives an original input signal and generates an analog input signal. The ADC converts the analog input signal to a digital input signal. The AIC generates a digital interference signal digital interference signal by performing an adaptive interference cancellation process according to the digital input signal. The DAC converts the digital interference signal to an analog interference signal. Finally, the analog interference signal is fed back to the AFE and cancelled from the original input signal in the AFE processor while performing the front end process, reducing the interference of the static interference from the leaking of a close-by transmitter during the front end process.

Abstract: Methods, systems, and apparatuses for Sidelink Discontinuous Reception (SL DRX) in a wireless communication system to avoid ambiguity on slot offset calculations on SL DRX. A method for a UE comprises performing a SL communication associated with a destination Identity (ID), having a SL DRX configuration associated with the SL communication, wherein the SL DRX configuration comprises at least an on-duration timer and a DRX cycle, deriving a first offset associated with the SL communication based on the destination ID and the DRX cycle, deriving a second offset associated with the SL communication based on the destination ID and a number of slots per subframe, starting the on-duration timer after a time period determined based on the second offset from the beginning of a subframe, wherein the subframe is determined based on at least the first offset, and monitoring Sidelink Control Information (SCI) when the on-duration timer is running.

Abstract: A radar signal processing system with a self-interference cancelling function includes an analog front end (AFE) processor, an analog to digital converter (ADC), an adaptive interference canceller (AIC), and a digital to analog converter (DAC). The AFE processor receives an original input signal and generates an analog input signal. The ADC converts the analog input signal to a digital input signal. The AIC generates a digital interference signal digital interference signal by performing an adaptive interference cancellation process according to the digital input signal. The DAC converts the digital interference signal to an analog interference signal. Finally, the analog interference signal is fed back to the AFE and cancelled from the original input signal in the AFE processor while performing the front end process, reducing the interference of the static interference from the leaking of a close-by transmitter during the front end process.

Abstract: The invention discloses an oscillator, including a voltage switching circuit, a voltage adjustment circuit and a frequency generation circuit. The voltage switching circuit receives an output voltage signal whereby the output voltage signal switches a first input voltage signal to a first voltage level signal and switches a second input voltage signal to a second voltage level signal. The voltage adjustment circuit receives the first voltage level signal and the second voltage level signal, whereby the first voltage level signal and the second voltage level signal generate the first adjustment voltage signal and the second adjustment voltage signal. The frequency generation circuit is connected to the voltage adjustment circuit, and receives the first adjustment voltage signal and the second adjustment voltage signal to generate the first output frequency signal and the second output frequency signal according to the first adjustment voltage signal and the second adjustment voltage signal.