Patents by Inventor Ming-Wen YEH

Ming-Wen YEH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12015013
    Abstract: A die stack structure including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a redistribution circuit structure is provided. The first semiconductor die includes a first semiconductor substrate including a first portion and a second portion, a first interconnect structure and a first bonding structure. The first interconnect structure is disposed on a top surface of the second portion, a lateral dimension of the first portion is greater than a lateral dimension of the top surface of the second portion. The second semiconductor die is disposed on the first semiconductor die and includes a second bonding structure, the second semiconductor die is electrically connected with the first semiconductor die through the first and second bonding structures. The insulating encapsulation is disposed on the first portion and laterally encapsulating the second portion and the second semiconductor die.
    Type: Grant
    Filed: February 21, 2022
    Date of Patent: June 18, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Chao-Wen Shih, Min-Chien Hsiao, Nien-Fang Wu, Sung-Feng Yeh, Tzuan-Horng Liu
  • Publication number: 20240194588
    Abstract: A semiconductor structure includes a first semiconductor substrate, a first interconnect structure disposed below the first semiconductor substrate, a through substrate via (TSV) penetrating through the first semiconductor substrate and extending into the first interconnect structure, and a first bonding conductor disposed below the first interconnect structure and electrically coupled to the TSV through the first interconnect structure. The TSV includes a first surface in the first interconnect structure and a second surface opposite to the first surface, and the first bonding conductor includes a first bonding surface facing away the first interconnect structure. In a view, a boundary of the first bonding surface of the first bonding conductor overlaps a boundary of the first surface of the TSV.
    Type: Application
    Filed: January 9, 2024
    Publication date: June 13, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Publication number: 20240153881
    Abstract: A method of forming semiconductor structure includes attaching backsides of top dies to a front side of a bottom wafer, the bottom wafer comprising a plurality of bottom dies; forming first conductive pillars on the front side of the bottom wafer adjacent to the top dies; forming a first dielectric material on the front side of the bottom wafer around the top dies and around the first conductive pillars; and dicing the bottom wafer to form a plurality of structures, each of the plurality of structures comprising at least one of the top dies and at least one of the bottom dies.
    Type: Application
    Filed: January 2, 2024
    Publication date: May 9, 2024
    Inventors: Chen-Hua Yu, Tzuan-Horng Liu, Ming-Fa Chen, Chao-Wen Shih, Sung-Feng Yeh
  • Publication number: 20240088279
    Abstract: A method for forming a semiconductor structure includes the steps of forming a stacked structure on a substrate, forming an insulating layer on the stacked structure, forming a passivation layer on the insulating layer, performing an etching process to form an opening through the passivation layer and the insulating layer to expose a portion of the stacked structure and an extending portion of the insulating layer, and forming a contact structure filling the opening and directly contacting the stacked structure, wherein the extending portion of the insulating layer is adjacent to a surface of the stacked structure directly contacting the contact structure.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 14, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Hua Chang, Po-Wen Su, Chih-Tung Yeh
  • Patent number: 11923437
    Abstract: A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsu-Hui Su, Chun-Hsiang Fan, Yu-Wen Wang, Ming-Hsi Yeh, Kuo-Bin Huang
  • Patent number: 11916012
    Abstract: A manufacturing method of a semiconductor structure is provided. A first semiconductor die includes a first semiconductor substrate, a first interconnect structure formed thereon, a first bonding conductor formed thereon, and a conductive via extending from the first interconnect structure toward a back surface of the first semiconductor substrate. The first semiconductor substrate is thinned to accessibly expose the conductive via to form a through semiconductor via (TSV). A second semiconductor die is bonded to the first semiconductor die. The second semiconductor die includes a second semiconductor substrate including an active surface facing the back surface of the first semiconductor substrate, a second interconnect structure between the second and the first semiconductor substrates, and a second bonding conductor between the second interconnect structure and the first semiconductor substrate and bonded to the TSV.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Publication number: 20170280844
    Abstract: A case assembly includes a first case, a second case, a moving mechanism and a block. The first case has an inner surface and a groove located at the inner surface. The second case includes a main part disposed on the first case and a fixing part disposed on the main part. The moving mechanism is pivoted to the inner surface. The block is pivoted to another end of the moving mechanism. The block is slidable between a fixed position and a detached position. When the block is located at the fixed position, the block restricts the fixing part so as to assemble the second case and the first case together. When the moving mechanism drives the block to the detached position, the fixing part is not restricted by the block, and the moving mechanism forces a part of the second case to separate from the first case.
    Type: Application
    Filed: August 15, 2016
    Publication date: October 5, 2017
    Applicant: TPV-INVENTA TECHNOLOGY CO.,LTD.
    Inventors: Yu-Ying TSENG, Ming-Wen YEH, Chia-Pang TANG, Jen-Hung HSIAO