Patents by Inventor Ming Wen
Ming Wen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240098932Abstract: A foldable electronic device, including a first body, a second body, an air valve movably disposed in the first body, at least one triggering member, and a hinge connecting the first body and the second body, is provided. The first body has multiple openings respectively located at two opposite surfaces. The triggering member is movably disposed in the first body and has a part exposed outside the first body. The air valve and the triggering member are mutually on moving paths of each other. The first body and the second body are rotated to be folded or unfolded relative to each other by the hinge. A part of the triggering member is suitable for bearing a force such that the triggering member drives the air valve, so that the air valve opens or closes the openings.Type: ApplicationFiled: July 19, 2023Publication date: March 21, 2024Applicant: Acer IncorporatedInventors: Hui-Ping Sun, Jui-Yi Yu, Chun-Hung Wen, Yen-Chou Chueh, Yu-Ming Lin, Chun-Hsien Chen
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Publication number: 20240084040Abstract: The present invention provides antibody or the antigen-binding portion thereof bind to carbohydrate antigen, such as Globo series antigens (e.g. Globo H, SSEA-4 or SSEA-3). Also disclosed herein are pharmaceutical compositions and methods for the inhibition of cancer cells in a subject in need thereof. The pharmaceutical compositions comprise an antibody or an antigen-binding portion thereof and at least one pharmaceutically acceptable carrier.Type: ApplicationFiled: February 9, 2022Publication date: March 14, 2024Inventors: Jiann-Shiun LAI, Hui-Wen CHANG, Yin-Chieh KUO, Chi-Sheng HSIA, Woan Eng CHAN, Ming-Tain LAI
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Publication number: 20240088236Abstract: In a method of manufacturing a semiconductor device, underlying structures comprising gate electrodes and source/drain epitaxial layers are formed, one or more layers are formed over the underlying structures, a hard mask layer is formed over the one or more layers, one or more first resist layers are formed over the hard mask layer, a first photo resist pattern is formed over the one or more first resist layers, a width of the first photo resist pattern is adjusted, the one or more first resist layers are patterned by using the first photo resist pattern as an etching mask, thereby forming a first hard mask pattern, and the hard mask layer is patterned by using the first hard mask pattern, thereby forming a second hard mask pattern.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Wen HSIAO, Chun-Yen TAI, Yen-Hsin LIU, Ming-Jhih KUO, Ming-Feng SHIEH
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Publication number: 20240088279Abstract: A method for forming a semiconductor structure includes the steps of forming a stacked structure on a substrate, forming an insulating layer on the stacked structure, forming a passivation layer on the insulating layer, performing an etching process to form an opening through the passivation layer and the insulating layer to expose a portion of the stacked structure and an extending portion of the insulating layer, and forming a contact structure filling the opening and directly contacting the stacked structure, wherein the extending portion of the insulating layer is adjacent to a surface of the stacked structure directly contacting the contact structure.Type: ApplicationFiled: November 27, 2023Publication date: March 14, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ming-Hua Chang, Po-Wen Su, Chih-Tung Yeh
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Patent number: 11929319Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.Type: GrantFiled: July 22, 2021Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Yu Huang, Han-Ping Pu, Ming-Kai Liu, Ting-Chu Ko, Yung-Ping Chiang, Chang-Wen Huang, Yu-Sheng Hsieh
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Patent number: 11920472Abstract: A reasonable millisecond time control method for excavation blasting of a tunnel is provided, and includes: acquiring physical mechanical parameters to establish a millisecond blasting model, and designing four dimensions blasting parameters of explosive quantity, hole number, inter-hole millisecond and inter-row millisecond; simulating, based on the millisecond blasting model, a blasting process of an explosive package using blasting parameters to obtain a blasting vibration curve; obtaining single-hole blasting vibration waveforms, solving a vibration synthesis curve through a vibration synthesis theory; comparing the vibration synthesis curve with the blasting vibration curve to obtain a coupling relationship of blasting parameters; determining a target group of explosive quantity and hole numbers, determining a target millisecond through the coupling relationship of blasting parameters, and relating a millisecond blasting control strategy to control, and it is used for tunneling project to reduce cut blasType: GrantFiled: September 20, 2023Date of Patent: March 5, 2024Assignees: CHINA RAILWAY ELEVENTH BUREAU GROUP CO., LTD, CHINA RAILWAY ELEVENTH BUREAU GROUP FOURTH ENGINEERING CO., LTD., WUJIU RAILWAY PASSENGER DEDICATED LINE HUBEI CO., LTD, CHINA RAILWAY FOURTH BUREAU GROUP CO., LTD, ANHUI CHINA RAILWAY ENGINEERING TECHNOLOGY SERVICE CO., LTD, WUHAN INSTITUTE OF GEOTECHNICAL MECHANICS, CHINESE ACADEMY OF SCIENCES, CHINA RAILWAY SOUTHWEST SCIENTIFIC RESEARCH INSTITUTE CO., LTDInventors: Jun Gao, Liyun Yang, Xiao Lin, Ming Zhang, kaiwen Liu, Xiaowei Zuo, Bin Zhou, Feng Wang, Yuxin Gao, Dan Xu, Ling Wang, Zhengyi Wang, Xiaokai Wen, Yongtai Wang, Huiling Xue
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Patent number: 11923437Abstract: A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.Type: GrantFiled: October 25, 2021Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsu-Hui Su, Chun-Hsiang Fan, Yu-Wen Wang, Ming-Hsi Yeh, Kuo-Bin Huang
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Patent number: 11916012Abstract: A manufacturing method of a semiconductor structure is provided. A first semiconductor die includes a first semiconductor substrate, a first interconnect structure formed thereon, a first bonding conductor formed thereon, and a conductive via extending from the first interconnect structure toward a back surface of the first semiconductor substrate. The first semiconductor substrate is thinned to accessibly expose the conductive via to form a through semiconductor via (TSV). A second semiconductor die is bonded to the first semiconductor die. The second semiconductor die includes a second semiconductor substrate including an active surface facing the back surface of the first semiconductor substrate, a second interconnect structure between the second and the first semiconductor substrates, and a second bonding conductor between the second interconnect structure and the first semiconductor substrate and bonded to the TSV.Type: GrantFiled: June 29, 2021Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
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Patent number: 11907745Abstract: Certain embodiments described herein are directed to methods and systems for adding one or more nodes to a first cluster including a first node in a computer system. A method performed by the first node comprises receiving a first request from a second node to join the first cluster. The method also comprises retrieving a first cluster configuration associated with the first cluster from a distributed database through a first database server (DBS) and creating a second cluster configuration using the first cluster configuration and information received from the second node as part of the request. The method further comprises populating a first one or more local trust stores of a first one or more processes executing on the first node with a second one or more security certificates of a second one or more processes executing on the second node. The method further comprises writing the second cluster configuration to the distributed database and returning the second cluster configuration to the second node.Type: GrantFiled: January 25, 2021Date of Patent: February 20, 2024Assignee: VMware, Inc.Inventors: Srinivas Neginhal, Medhavi Dhawan, Vjekoslav Brajkovic, Cheng Zhang, Jiaqi Chen, David Tsai, Maithem Munshed, Zeeshan Lokhandwala, Ming Wen, Ragnar Edholm, Rajneesh Bajpai
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Patent number: 11862690Abstract: In a method of manufacturing a semiconductor device, underlying structures comprising gate electrodes and source/drain epitaxial layers are formed, one or more layers are formed over the underlying structures, a hard mask layer is formed over the one or more layers, one or more first resist layers are formed over the hard mask layer, a first photo resist pattern is formed over the one or more first resist layers, a width of the first photo resist pattern is adjusted, the one or more first resist layers are patterned by using the first photo resist pattern as an etching mask, thereby forming a first hard mask pattern, and the hard mask layer is patterned by using the first hard mask pattern, thereby forming a second hard mask pattern.Type: GrantFiled: April 23, 2021Date of Patent: January 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Wen Hsiao, Chun-Yen Tai, Yen-Hsin Liu, Ming-Jhih Kuo, Ming-Feng Shieh
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Publication number: 20230327743Abstract: The present invention provides a control method of an electronic device is disclosed, wherein the electronic device includes a first antenna and a second antenna. The control method includes the steps of: setting one of the first antenna and the second antenna as a default antenna; receiving a plurality of packets within an interval; for each of the plurality of packets, comparing a signal strength corresponding to the first antenna and a signal strength of the second antenna to generate a first comparison result; updating a first value or a second value according to the first comparison result; wcomparing the first value and the second value to generate a second comparison result when running out the interval; and selecting one of the first antenna and the second antenna to be the default antenna according to the second comparison result.Type: ApplicationFiled: March 20, 2023Publication date: October 12, 2023Applicant: MEDIATEK INC.Inventors: Che-Wei Huang, Yu-Ming Wen, Po-Hsun Huang, Gui-Lin Chen, Yen-Shuo Lu, Ting-Che Tseng
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Publication number: 20230289144Abstract: The present invention is based on the data value and data timing attributes realizations and provides an explicitly defined definite or fixed method for constructing a computing system software consisting of (1). A definite system development method; (2). A definite safety relevant system development method in the furthermore manner; (3) the specific and definite criteria to measure the software and the safety. Said method is based on the exclusive disclosure that is: computing system functionalities can be fully represented by the data comprising Input Data, Middle Data and Output Data, in which the Output Data represent fully the system functionalities under the input data from the system black-box point of view, the Middle Data represent fully the middle functionalities that are transporting and transforming the Input Data to the Output Data. In the system, each data has two and only two systematic attributes: data value and data timing attributes.Type: ApplicationFiled: February 12, 2023Publication date: September 14, 2023Inventor: Jin Ming Wen
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Publication number: 20230269653Abstract: A rerouting method and apparatus and a communication device. The method comprises: a first communication node obtains target information, wherein the target information comprises at least one of the following: link state information of a backhaul path associated with the first communication node, and identification information of the backhaul path; and the first communication node determines a target backhaul path according to the target information.Type: ApplicationFiled: May 1, 2023Publication date: August 24, 2023Applicant: VIVO MOBILE COMMUNICATION CO., LTD.Inventors: Ming WEN, Jinhua LIU
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Publication number: 20230138947Abstract: A random access method and apparatus, and a network-side device are disclosed in the embodiments of this application, to resolve a problem that a behavior of an IAB node when receiving a BI is not defined in the related art, affecting the communication effectiveness. The method may be applied to an IAB node and include: performing at least one of the following in a case of receiving a backoff indicator during a random access process initiated through a first random access resource: generating a time delay according to the backoff indicator, and initiating the random access process again after the time delay expires; and ignoring the backoff indicator, and initiating the random access process again through the first random access resource or a second random access resource.Type: ApplicationFiled: December 29, 2022Publication date: May 4, 2023Inventors: Ming WEN, Xiaodong YANG, Jinhua LIU
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Publication number: 20230116034Abstract: The present invention provides a explicitly defined method for implementing some of reliabilities for a computing system under development comprising FMEA, systematic error detection said method is based on the exclusive disclosure that is: a computing system functionalities can be fully represented by the data comprising Input Data, Middle Data and Output Data, in which the Output Data represent fully the system functionalities under the input data from the system black-box point of view, the Middle Data represent fully the middle functionalities that are transporting and transforming the Input Data to the Output Data. So, the development activities that are against the functionalities, such as FMEA, systematic error detection will be complete, consistent, accurate and efficient if they are applied only for the data.Type: ApplicationFiled: September 27, 2021Publication date: April 13, 2023Inventor: Jin Ming Wen
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Publication number: 20230016053Abstract: Embodiments of the present disclosure disclose a cell selection or reselection method and a device, to resolve a problem that a terminal device cannot effectively and rapidly access a cell without taking a slice of the cell into consideration when performing cell selection or reselection. The method may be performed by a terminal device, and includes: receiving a MIB message from a cell; in a case of determining, based on the MIB message, that the cell can be a candidate access cell, reading a SIB message of the cell, where the SIB message includes slice information of the cell; and selecting one slice from slices of the cell to access based on slice information supported by the terminal device and the slice information of the cell.Type: ApplicationFiled: September 21, 2022Publication date: January 19, 2023Inventors: Ming WEN, Kimba Dit Adamou BOUBACAR
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Publication number: 20230017114Abstract: A random access method and a terminal device are provided. The method may be performed by the terminal device and includes: receiving an SIB message from a cell, where the SIB message includes slice information of the cell and a mapping relationship between the slice information and at least one of the following: a PRACH resource or a preamble; selecting a slice based on the slice information; and selecting, based on the mapping relationship, a preamble and a PRACH resource that are corresponding to the slice to initiate a random access procedure.Type: ApplicationFiled: September 29, 2022Publication date: January 19, 2023Applicant: VIVO MOBILE COMMUNICATION CO., LTD.Inventors: Ming WEN, Boubacar KIMBA DIT ADAMOU
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Publication number: 20220406661Abstract: In a method of manufacturing a semiconductor device, underlying structures comprising gate electrodes and source/drain epitaxial layers are formed, one or more layers are formed over the underlying structures, a hard mask layer is formed over the one or more layers, a groove pattern is formed in the hard mask layer, one or more first resist layers are formed over the hard mask layer having the groove pattern, a first photo resist pattern is formed over the one or more first resist layers, the one or more first resist layers are patterned by using the first photo resist pattern as an etching mask, thereby forming a first hard mask pattern, and the hard mask layer with the groove pattern are patterned by using the first hard mask pattern, thereby forming a second hard mask pattern.Type: ApplicationFiled: June 18, 2021Publication date: December 22, 2022Inventors: Chuan-Hui LU, Ming-Feng SHIEH, Ming-Jhih KUO, Ming-Wen HSIAO
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Publication number: 20220344478Abstract: In a method of manufacturing a semiconductor device, underlying structures comprising gate electrodes and source/drain epitaxial layers are formed, one or more layers are formed over the underlying structures, a hard mask layer is formed over the one or more layers, one or more first resist layers are formed over the hard mask layer, a first photo resist pattern is formed over the one or more first resist layers, a width of the first photo resist pattern is adjusted, the one or more first resist layers are patterned by using the first photo resist pattern as an etching mask, thereby forming a first hard mask pattern, and the hard mask layer is patterned by using the first hard mask pattern, thereby forming a second hard mask pattern.Type: ApplicationFiled: April 23, 2021Publication date: October 27, 2022Inventors: Ming-Wen HSIAO, Chun-Yen TAI, Yen-Hsin LIU, Ming-Jhih KUO, Ming-Feng SHIEH
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Patent number: D1020713Type: GrantFiled: August 19, 2021Date of Patent: April 2, 2024Assignee: COMPAL ELECTRONICS, INC.Inventors: Yi-Wen Chen, Ming-Sheng Shih