Abstract: A backlight module and a driving circuit are provided. The driving circuit includes a plurality of current sources and a current switching unit. The current sources provide a plurality of driving currents. The current switching unit is coupled between a plurality of light emitting element strings and the current sources for transmitting the driving currents to the light emitting element strings, and switching the driving currents received by the light emitting element strings by timing. Therefore, the brightness of the light emitting element strings can be equalized.

Abstract: A non-linear inductor is disclosed herein. The non-linear inductor includes a first magnetic core, a second magnetic core, a third magnetic core, a fourth magnetic core, a fifth magnetic core and a coil unit. The first and the second magnetic core are disposed in parallel. The third magnetic core, the fourth magnetic core and the fifth magnetic core are all vertically disposed between the first and the second magnetic core. The fourth magnetic core is vertically disposed between the first and the second magnetic core. The fourth and the fifth magnetic core are disposed at both sides of the third magnetic core in parallel. The coil unit winds around the third magnetic core. A magnetic resistance of the fourth magnetic core passed through by an inductive magnetic flux is different from a magnetic resistance of the fifth magnetic core passed through by the inductive magnetic flux.

Abstract: An LCD (Liquid Crystal Display) Device of improvement of flicker upon switching frame rate and method for the same are proposed. The LCD device includes a pixel matrix, a timing controller and a gate driver. The timing controller outputs a first Gate-On-Enable signal to the gate driver, when the LCD device displays frame according to a first frame rate. When the first frame rate is switched to a second frame rate, the timing controller outputs a second Gate-On-Enable signal to the gate driver to cause a charge time of the pixel matrix to be unchanged. It is appreciated that a pulse width of the second Gate-On-Enable signal is equal to a summation of a pulse width of the first Gate-On-Enable signal and an adjusted pulse width.

Abstract: A backlight module and a driving circuit are provided. The driving circuit includes a plurality of current sources and a current switching unit. The current sources provide a plurality of driving currents. The current switching unit is coupled between a plurality of light emitting element strings and the current sources for transmitting the driving currents to the light emitting element strings, and switching the driving currents received by the light emitting element strings by timing. Therefore, the brightness of the light emitting element strings can be equalized.

Abstract: The present invention discloses an source driver circuit scheme for displayer, which comprises a shifter register to register data signal, a line buffer coupled with said shifter register to latch the data signal, a level shifter coupled with line buffer to level output electrical potential, a digital-to-analog converter (DAC) to convert digital signal to analog signal, an output buffer coupled with said digital-to-analog converter (DAC) to output converted signal, and an output control circuit coupled with output buffer. Said output control circuit comprises a D flip-flop and CMOS switching element to output a LP_out signal and control the data signal output of the source driver IC to avoid the power-on noise of the displayer.

Abstract: A LCD Device of improvement of flicker upon switching frame rate and method for the same are proposed. The LCD device includes a pixel matrix, a timing controller and a gate driver. The timing controller outputs a first Gate-On-Enable signal to the gate driver, when the LCD device displays frame according to a first frame rate. When the first frame rate is switched to a second frame rate, the timing controller outputs a second Gate-On-Enable signal to the gate driver to cause a charge time of the pixel matrix unchanged. It is appreciated that a pulse width of the second Gate-On-Enable signal is equal to a summation of a pulse width of the first Gate-On-Enable signal and an adjusted pulse width.

Abstract: A gate driving circuit and a power control circuit are disclosed. The gate driving circuit includes a gate driver and the power control circuit. The gate driver is adapted for receiving a starting signal and sequentially outputting a plurality of scan signals accordingly. The power control circuit includes a delay circuit, a level shifter and a switch unit. The delay circuit is adapted for receiving and delaying the starting signal for a predetermined period and then outputting the delayed starting signal. The level shifter receives and adjusts a voltage level of the delayed starting signal, and outputs a starting voltage accordingly. The switch unit provides the first power to the gate driver after being delayed for the predetermined period according to the starting voltage.

Abstract: The present invention discloses an source driver circuit scheme for displayer, which comprises a shifter register to register data signal, a line buffer coupled with said shifter register to latch the data signal, a level shifter coupled with line buffer to level output electrical potential, a digital-to-analog converter (DAC) to convert digital signal to analog signal, an output buffer coupled with said digital-to-analog converter (DAC) to output converted signal, and an output control circuit coupled with output buffer. Said output control circuit comprises a D flip-flop and CMOS switching element to output a LP_out signal and control the data signal output of the source driver IC to avoid the power-on noise of the displayer.

Abstract: A gate driving circuit and a power control circuit are disclosed. The gate driving circuit includes a gate driver and the power control circuit. The gate driver is adapted for receiving a starting signal and sequentially outputting a plurality of scan signals accordingly. The power control circuit includes a delay circuit, a level shifter and a switch unit. The delay circuit is adapted for receiving and delaying the starting signal for a predetermined period and then outputting the delayed starting signal. The level shifter receives and adjusts a voltage level of the delayed starting signal, and outputs a starting voltage accordingly. The switch unit provides the first power to the gate driver after being delayed for the predetermined period according to the starting voltage.

Abstract: An apparatus for digital-to-analog conversion and the method thereof is disclosed, wherein the complete scale-tuned levels of more bits may be presented with an output of less bits. The apparatus comprises a timing controller, a scale-tuned circuit and a digital-to-analog converter. The timing controller receives an a-bit grayscale value, and outputs a selection signal and a b-bit control signal, wherein a, b are both positive integers and a>b>=1. The selection signal has two states: if the grayscale value is less than or equal to 2a?2c, wherein c is equal to a?b, the selection signal is in a first state; and if the grayscale value is equal to 2a?2c+n, wherein n is an integer and 0<n<2c, the selection signal has a probability of n/2c to be in a second state, and has a probability of 1?n/2c to be in the first state.