Abstract: A post over-erase correction (POEC) method with an auto-adjusting verification mechanism and a leakage degree detection function detects gm degradation or leakage degree of flash cells before or after entering the POEC process. When a preset condition is satisfied, the auto-adjusting verification mechanism of the POEC is switched on to further reduce leakage current. After cycling, the POEC repairs Vt of over-erased cells to a higher level to solve leakage issues. The erase shot count increases due to slower erase speeds after cycling. Therefore, the cycling degree of flash cells is detected by observing the shot number that the erase operation used. When the leakage phenomenon becomes serious, the bit line (BL) leakage current, amount of repaired BLs, and over-erase correction (OEC) shot number will increase during the OEC procedure. Therefore, the leakage degree of flash cells can be detected by inspecting the above data.

Abstract: A post over-erase correction (POEC) method with an auto-adjusting verification mechanism and a leakage degree detection function detects gm degradation or leakage degree of flash cells before or after entering the POEC process. When a preset condition is satisfied, the auto-adjusting verification mechanism of the POEC is switched on to further reduce leakage current. After cycling, the POEC repairs Vt of over-erased cells to a higher level to solve leakage issues. The erase shot count increases due to slower erase speeds after cycling. Therefore, the cycling degree of flash cells is detected by observing the shot number that the erase operation used. When the leakage phenomenon becomes serious, the bit line (BL) leakage current, amount of repaired BLs, and over-erase correction (OEC) shot number will increase during the OEC procedure. Therefore, the leakage degree of flash cells can be detected by inspecting the above data.

Abstract: An erase voltage compensation mechanism for group erase mode with bit line leakage detection comprises performing a block erase operation by applying an erase voltage. Continue block erasing until bit line leakage is detected upon which the erase voltage is latched and over-erase correction is performed. A compensation voltage value is calculated by finding the difference between an upper bound of a threshold voltage distribution and an erase verify point when the bit line leakage was detected. The latched erase voltage is increased by the compensation voltage to create a compensated voltage. A group erase operation is performed and the group address is incremented by 1 and the compensated voltage value is loaded. Then the group erase operation is performed on the next group. The address is incremented, the compensated voltage is loaded, and the group erase operation is performed until the group is the last group.

Abstract: An optical sensing circuit has a plurality of optical sensing units arranged so that the optical sensing circuit is ambient light insensitive or sensitive to light within certain spectrum. The sensitive spectra corresponding to the plurality of optical sensing units are different from one another.

Abstract: An optical sensing circuit has a plurality of optical sensing units arranged so that the optical sensing circuit is ambient light insensitive or sensitive to light within certain spectrum. The sensitive spectra corresponding to the plurality of optical sensing units are different from one another.