Abstract: A transistor device disposed on a substrate and including a semiconductor layer, a first gate, a second gate, and two source drain electrodes is provided. The semiconductor layer is disposed on the substrate and has a channel region, two lightly-doped regions, and two source drain regions. Each of the two lightly-doped regions has a first boundary adjoined to the channel region and a second boundary adjoined to one of the two source drain regions. The first gate is extended over the channel region of the semiconductor layer, wherein an edge of the first gate is aligned with the first boundary. The second gate is stacked on the first gate and is in contact with the first gate, wherein in a thickness direction, the second gate is overlapped with the two lightly-doped regions. The two source drain electrodes are respectively in contact with the two source drain regions.

Abstract: A transistor device disposed on a substrate and including a semiconductor layer, a first gate, a second gate, and two source drain electrodes is provided. The semiconductor layer is disposed on the substrate and has a channel region, two lightly-doped regions, and two source drain regions. Each of the two lightly-doped regions has a first boundary adjoined to the channel region and a second boundary adjoined to one of the two source drain regions. The first gate is extended over the channel region of the semiconductor layer, wherein an edge of the first gate is aligned with the first boundary. The second gate is stacked on the first gate and is in contact with the first gate, wherein in a thickness direction, the second gate is overlapped with the two lightly-doped regions. The two source drain electrodes are respectively in contact with the two source drain regions.

Abstract: A diaphragm piezoresistive pressure sensor includes: a base member; a diaphragm including a middle portion and a surrounding portion surrounding the middle portion; a spacer disposed between and cooperating with the base member and the diaphragm to define a cavity thereamong; an inner abutment member disposed in the cavity and spaced apart from the base member by a clearance; and a piezoresistive sensor unit embedded in the diaphragm. The spacer surrounds and is spaced apart from the inner abutment member. At least one of the inner abutment member and the middle portion of the diaphragm defines a chamber therebetween.

Abstract: The present invention related to a cyclic microfluidic chip that comprises a substrate and a top cover. The substrate having a surface that provides a chamber providing location of a first cell and having a first microchannel, a second microchannel being wrapped around the outside of the chamber and comprising an ECM inlet and an ECM outlet; and a third microchannel being wrapped around the outside of the second microchannel and comprising an cell inlet and an cell outlet to provide a second cell input and output respectively. The top cover comprises a fourth microchannel to provide a medium input and a medium output.

Abstract: A diaphragm piezoresistive pressure sensor includes: a base member; a diaphragm including a middle portion and a surrounding portion surrounding the middle portion; a spacer disposed between and cooperating with the base member and the diaphragm to define a cavity thereamong; an inner abutment member disposed in the cavity and spaced apart from the base member by a clearance; and a piezoresistive sensor unit embedded in the diaphragm. The spacer surrounds and is spaced apart from the inner abutment member. At least one of the inner abutment member and the middle portion of the diaphragm defines a chamber therebetween.

Abstract: A method for fabricating a pixel structure is provided. A patterned semiconductor layer including a lower electrode, a doped source region, a doped drain region and a channel region is formed on a substrate. A gate dielectric layer is formed on the patterned semiconductor layer. A patterned first metal layer including a gate electrode, a scan line and a common electrode is formed on the gate dielectric layer, wherein the channel region is disposed below the gate electrode. A first dielectric layer and a first passivation layer are sequentially formed on the patterned first metal layer. A patterned second metal layer including a source, a drain and a data line is formed on the first passivation layer, wherein the data line is disposed above the common electrode, and the first dielectric layer and the first passivation layer are disposed between the data line and the common electrode.

Abstract: An organic light emitting diode (OLED) display panel and a method of forming a polysilicon channel layer thereof are provided. In the method, firstly, a substrate having a polysilicon layer disposed thereon is provided. Then, a dopant atom not selected from the IIIA group and the VA group is doped inside the polysilicon layer to form a polysilicon channel layer.

Abstract: A fabrication method of a pixel structure includes providing a substrate. A semiconductor layer and a first conductive layer are formed on the substrate in sequence and patterned to form a semiconductor pattern and a data line pattern. A gate insulation layer and a second conductive layer are formed on the substrate in sequence and patterned to form a gate pattern and a scan line pattern connected to each other. A source region, a drain region, a channel region, and a lightly doped region are formed in the semiconductor pattern. A third conductive layer formed on the substrate is patterned to form a source pattern and a drain pattern. A protective layer is formed on the substrate and patterned to form a contact window to expose the drain pattern. A pixel electrode electrically connected to the drain pattern through the contact window is formed on the protective layer.

Abstract: A fabrication method of a pixel structure includes providing a substrate. A semiconductor layer and a first conductive layer are formed on the substrate in sequence and patterned to form a semiconductor pattern and a data line pattern. A gate insulation layer and a second conductive layer are formed on the substrate in sequence and patterned to form a gate pattern and a scan line pattern connected to each other. A source region, a drain region, a channel region, and a lightly doped region are formed in the semiconductor pattern. A third conductive layer formed on the substrate is patterned to form a source pattern and a drain pattern. A protective layer is formed on the substrate and patterned to form a contact window to expose the drain pattern. A pixel electrode electrically connected to the drain pattern through the contact window is formed on the protective layer.

Abstract: A pixel structure and a fabrication method thereof are provided, wherein a semiconductor pattern and a data line are defined simultaneously by performing a half-tone or grey-tone masking process. In addition, a self-alignment manner is further adopted to fabricate a lightly doped region with symmetric lengths on two sides of a channel region through steps such as photoresist ashing and etching, so as to prevent the problem of misalignment of mask generated when a mask is used to define the lightly doped region in the conventional art. Furthermore, a source pattern and a drain pattern are made to directly contact a source region and a drain region of the semiconductor pattern, such that a process of fabricating a via is omitted. Besides, in the present invention, a common line pattern surrounding the peripheral of the pixel region is also formed to improve the aperture ratio of the pixel structure.

Abstract: An organic light emitting diode (OLED) display panel and a method of forming a polysilicon channel layer thereof are provided. In the method, firstly, a substrate having a polysilicon layer disposed thereon is provided. Then, a dopant atom not selected from the IIIA group and the VA group is doped inside the polysilicon layer to form a polysilicon channel layer.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The manufacturing method can form a structure of a thin film transistor (TFT) having a symmetric lightly doped region, and thus provide superior operation reliability and electrical performance. In addition, the manufacturing method forms gate patterns of different TFTs by the same mask process and thereby avoids the misalignment of masks so as to improve the processing yield and reduce the manufacturing cost.

Abstract: A pixel structure and a fabrication method thereof are provided, wherein a semiconductor pattern and a data line are defined simultaneously by performing a half-tone or grey-tone masking process. In addition, a self-alignment manner is further adopted to fabricate a lightly doped region with symmetric lengths on two sides of a channel region through steps such as photoresist ashing and etching, so as to prevent the problem of misalignment of mask generated when a mask is used to define the lightly doped region in the conventional art. Furthermore, a source pattern and a drain pattern are made to directly contact a source region and a drain region of the semiconductor pattern, such that a process of fabricating a via is omitted. Besides, in the present invention, a common line pattern surrounding the peripheral of the pixel region is also formed to improve the aperture ratio of the pixel structure.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The manufacturing method can form a structure of a thin film transistor (TFT) having a symmetric lightly doped region, and thus provide superior operation reliability and electrical performance. In addition, the manufacturing method forms gate patterns of different TFTs by the same mask process and thereby avoids the misalignment of masks so as to improve the processing yield and reduce the manufacturing cost.

Abstract: An organic light emitting diode (OLED) display panel and a method of forming a polysilicon channel layer thereof are provided. In the method, firstly, a substrate having a polysilicon layer disposed thereon is provided. Then, a dopant atom not selected from the IIIA group and the VA group is doped inside the polysilcon layer to form a polysilicon channel layer.

Abstract: A method of forming a CMOS transistor on a substrate is provided, wherein the method requires only two implanting procedures to form all source/drain and light doped region. First, the source/drain of an NMOS transistor is formed by using a photoresist layer which covers up the source/drain of a PMOS transistor as a mask with a phosphorus dopant being implanted into. Next, the lightly doped region of an NMOS transistor and the source/drain of a PMOS transistor are formed by using a photoresist layer which covers up the source/drain of an NMOS transistor as well as the gate as masks with a boron dopant being implanted into. Of which, the dosage of the boron dopant is smaller than that of the phosphorus dopant.

Abstract: A method of forming a CMOS transistor on a substrate is provided, wherein the method requires only two implanting procedures to form all source/drain and light doped region. First, the source/drain of an NMOS transistor is formed by using a photoresist layer which covers up the source/drain of a PMOS transistor as a mask with a phosphorus dopant being implanted into. Next, the lightly doped region of an NMOS transistor and the source/drain of a PMOS transistor are formed by using a photoresist layer which covers up the source/drain of an NMOS transistor as well as the gate as masks with a boron dopant being implanted into. Of which, the dosage of the boron dopant is smaller than that of the phosphorus dopant.

Abstract: A method for transforming an amorphous silicon layer into a polysilicon layer is disclosed. The method includes following steps: providing an amorphous silicon substrate, doping the amorphous silicon substrate with an inert gas atom, and increasing the temperature of the surface of the amorphous silicon substrate by heat treatment or thermal process.

Abstract: The present invention relates generally to a magnet motor, and having being provided the driven power of the electromagnet motor for electric vehicles, wherein, it has provided with a wireless coil whole rotator, which the upper part has been constructed with an equal angle, a power perpetual magnet is provided. At least one set of a magnet pole coil is formed into an electromagnet pole module and a circuit control unit. Using the perpetual magnet and the less electricity consumption of an electric magnet pole generates the repelling torque, accomplishing the object of the turning rotator to generate power. Either it is coupled with a simple or a complex structure; it can apply to be the driven motor of a bicycle, a motorcycle and a car. Moreover, it can greatly reduce the consumption of the vehicle battery electricity, and make it to be an environmental protection and practical vehicle means.