Abstract: An inverter-based comparator, powered between a first supply voltage and a second supply voltage being lower than the first supply voltage, includes a first inverter branch composed of at least one first P-type transistor and at least one first N-type transistor; and a second inverter branch composed of at least one second P-type transistor, at least one second N-type transistor and at least two tuning switches. The first inverter branch and the second inverter branch are configured to compare an input voltage with an internal trigger point, thereby generating a compare voltage at an interconnected node. One of the at least two tuning switches is controlled to isolate the first supply voltage and another is controlled to isolate the second supply voltage to compensate for trigger point shifting.

Abstract: A system includes a high bandwidth memory (HBM) arranged into portions including memory cells, the HBM further including a differentiated dynamic voltage and frequency scaling (DDVFS) device to perform the following: for a first set of one or more of the memory cells in a first one of the portions, the first set including a first one of the memory cells, controlling a temperature of the first set based on one or more first environmental signals corresponding to at least a first transistor in the first memory cell; and for a second set of one or more of the memory cells in a second one of the portions, the second set including a second one of memory cells, controlling a temperature of the second set based on one or more second environmental signals corresponding to at least a second transistor in the second memory cell.

Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.

Abstract: An inverter-based comparator includes an output stage circuit including a P-type output transistor and an N-type output transistor; a first inverter having a first transition voltage with an input node coupled to an input voltage and an output node generating a first inverted voltage and coupled to a gate of the N-type output transistor; and a second inverter having a second transition voltage with an input node coupled to the input voltage and an output node generating a second inverted voltage and coupled to a gate of the P-type output transistor. The first inverter and the second inverter each includes an inverter that includes a first inverter branch composed of at least one first P-type transistor and at least one first N-type transistor; and a second inverter branch composed of at least one second P-type transistor, at least one second N-type transistor and at least two tuning switches.

Abstract: An inverter-based comparator, powered between a first supply voltage and a second supply voltage being lower than the first supply voltage, includes a first inverter branch composed of at least one first P-type transistor and at least one first N-type transistor; and a second inverter branch composed of at least one second P-type transistor, at least one second N-type transistor and at least two tuning switches. The first inverter branch and the second inverter branch are configured to compare an input voltage with an internal trigger point, thereby generating a compare voltage at an interconnected node. One of the at least two tuning switches is controlled to isolate the first supply voltage and another is controlled to isolate the second supply voltage to compensate for trigger point shifting.

Abstract: A system includes a high bandwidth memory (HBM) arranged into portions including memory cells, the HBM further including a differentiated dynamic voltage and frequency scaling (DDVFS) device to perform the following: for a first set of one or more of the memory cells in a first one of the portions, the first set including a first one of the memory cells, controlling a temperature of the first set based on one or more first environmental signals corresponding to at least a first transistor in the first memory cell; and for a second set of one or more of the memory cells in a second one of the portions, the second set including a second one of memory cells, controlling a temperature of the second set based on one or more second environmental signals corresponding to at least a second transistor in the second memory cell.

Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.

Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.

Abstract: A system includes: a high bandwidth memory (HBM) including a first sensing unit configured to generate one or more first environmental signals corresponding to a first transistor in a first memory cell, and a second sensing unit configured to generate one or more second environmental signals corresponding to a second transistor in a second memory cell; and a differentiated dynamic voltage and frequency scaling (DDVFS) device configured to perform the following (1) for a first set of the memory cells which includes the first memory cell, controlling temperature by adjusting one or more first transistor-temperature-affecting (TTA) parameters of the first set based on the one or more first environmental signals, and (2) for a second set of the memory cells which includes the second memory cell, controlling temperature by adjusting one or more second TTA parameters of the second set based on the one or more second environmental signals.

Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.

Abstract: Various implementations described herein are directed to multi-stage system. The system may include a first stage having a current bias generator that generates a biasing current. The system may include a second stage that is coupled to the first stage, and the second stage may include a load that utilizes the biasing current generated by the current bias generator.

Abstract: Subject matter disclosed herein may relate to detecting wireless signals and/or signal packets and may relate more particularly to detecting wireless signals and/or signal packets at energy-harvesting devices.

Abstract: A system includes: a high bandwidth memory (HBM) including a first sensing unit configured to generate one or more first environmental signals corresponding to a first transistor in a first memory cell, and a second sensing unit configured to generate one or more second environmental signals corresponding to a second transistor in a second memory cell; and a differentiated dynamic voltage and frequency scaling (DDVFS) device configured to perform the following (1) for a first set of the memory cells which includes the first memory cell, controlling temperature by adjusting one or more first transistor-temperature-affecting (TTA) parameters of the first set based on the one or more first environmental signals, and (2) for a second set of the memory cells which includes the second memory cell, controlling temperature by adjusting one or more second TTA parameters of the second set based on the one or more second environmental signals.

Abstract: Subject matter disclosed herein may relate to detecting wireless signals and/or signal packets and may relate more particularly to detecting wireless signals and/or signal packets at energy-harvesting devices.

Abstract: Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has a step-down converter coupled to an oscillator between a first voltage supply and a second voltage supply. The second stage is coupled to the first stage, and the second stage has a current bias generator coupled to a diode-connected transistor between the first voltage supply and the second voltage supply. The second stage provides an intermediate voltage to the first stage.

Abstract: Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has a step-down converter coupled to an oscillator between a first voltage supply and a second voltage supply. The second stage is coupled to the first stage, and the second stage has a current bias generator coupled to a diode-connected transistor between the first voltage supply and the second voltage supply. The second stage provides an intermediate voltage to the first stage.

Abstract: Various implementations described herein are directed to multi-stage system. The system may include a first stage having a current bias generator that generates a biasing current. The system may include a second stage that is coupled to the first stage, and the second stage may include a load that utilizes the biasing current generated by the current bias generator.

Abstract: Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has a step-down converter coupled to an oscillator between a first voltage supply and a second voltage supply. The second stage is coupled to the first stage, and the second stage has a current bias generator coupled to a diode-connected transistor between the first voltage supply and the second voltage supply. The second stage provides an intermediate voltage to the first stage.

Abstract: Various implementations described herein are directed to a device having a voltage regulator that uses a modulator to adjust an output voltage. The device may include a time-to-digital converter that measures a timing delay of a logic chain, compares the timing delay to a reference delay to determine a timing delay error, and provides the timing delay error to the modulator for adjusting the output voltage.

Abstract: Various implementations described herein refer to a method for providing an integrated circuit with a real-time clock source. The method may include generating a real-time clock signal for the integrated circuit with the real-time clock source. The method may include selectively adjusting clock frequency of the real-time clock signal to save power in the integrated circuit.