Patents by Inventor Ming Yang Wang

Ming Yang Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200343349
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a first source/drain region, a second source/drain region, first source/drain contact and a first dielectric spacer liner. The gate structure is over the semiconductor substrate. The first source/drain region and the second source/drain region are in the semiconductor substrate and respectively on opposite sides of the gate structure. The first source/drain contact is over the first source/drain region. The first dielectric spacer liner lines a sidewall of the first source/drain contact and extends into the first source/drain region.
    Type: Application
    Filed: July 11, 2020
    Publication date: October 29, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Cheng HUNG, Kei-Wei CHEN, Yu-Sheng WANG, Ming-Ching CHUNG, Chia-Yang WU
  • Patent number: 10792904
    Abstract: A method for bonding a first component to a second component includes placing the first and second components in a cavity. Each of the first and second components has a bonding portion, and the bonding portion of the first component faces the bonding portion of the second component. A supercritical fluid is then introduced into the cavity with a temperature of 40-400° C. and a pressure of 1,500-100,000 psi, and a pressure of 4-100,000 psi is applied on both the first and second components, assuring the bonding portion of the first component bond to the bonding portion of the second component. Moreover, a method for separating a first component from a second component includes placing a composite in a cavity. The composite includes the first component, the second component and a connecting layer by which the first component joins to the second component. The supercritical is then introduced into the cavity.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: October 6, 2020
    Assignee: NATIONAL SUN YAT-SEN UNIVERSITY
    Inventors: Ting-Chang Chang, Chih-Cheng Shih, Ming-Hui Wang, Wen-Chung Chen, Chih-Yang Lin
  • Publication number: 20200249101
    Abstract: A thermal sensor package for earbuds includes two thermopile sensor elements on a single thermopile sensor chip, and the two thermopile sensor elements are separated by a block wall of a cap. One of the thermopile sensor elements senses external infrared thermal radiation through a window of the cap, and the other thermopile sensor element senses internal infrared thermal radiation from a package structure as a basis for correcting compensation. Therefore, the foregoing thermal sensor package for earbuds can quickly correct a measurement error caused by the package structure to improve the measurement accuracy. In addition, the forgoing thermal sensor package for earbuds has a simple packaging step and is easy to arrange a silicon based infrared lens to expand its application.
    Type: Application
    Filed: June 14, 2019
    Publication date: August 6, 2020
    Inventors: Chein-Hsun WANG, Ming LE, Yu-Chih LIANG, Tung Yang LEE, Chih-Yung TSAI
  • Patent number: 10714576
    Abstract: A device includes an epitaxy structure having a recess therein, a dielectric layer over the epitaxy structure, the dielectric layer having a contact hole communicating with the recess, a dielectric spacer liner (DSL) layer on a sidewall of the recess, a barrier layer on the DSL layer, and a conductor. The DSL layer has an opening. The DSL layer extends further into the epitaxy structure than the barrier layer. The conductor is disposed in the contact hole and electrically connected to the epitaxy feature through the opening of the DSL layer.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: July 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Cheng Hung, Kei-Wei Chen, Yu-Sheng Wang, Ming-Ching Chung, Chia-Yang Wu
  • Publication number: 20200215426
    Abstract: A self-adhesive stacked set including a plurality of stacked bodies is provided. The plurality of stacked bodies form a three-dimensional geometry, and a top view shape of the plurality of stacked bodies includes a triangle and a quadrangle. Each of the stacked bodies includes a plurality of stacked layers, and the plurality of stacked layers are stacked on each other. A rear surface of each of the stacked layers has an adhesive region, and the plurality of stacked layers are stuck to each other via the adhesive region.
    Type: Application
    Filed: March 7, 2019
    Publication date: July 9, 2020
    Applicant: Taiwan Hopax Chemicals Mfg. Co., Ltd.
    Inventors: Mei-Lin Kuo, Ming-Yang Li, Tzu-Jung Wang, Kai-Wei Shih, Shu-Wei Ho
  • Patent number: 10598776
    Abstract: An electronic device includes a clock generating circuit, a receiving circuit and a training circuit. The clock generating circuit generates a sampling clock signal, a phase-early sampling clock signal and a phase-late sampling clock signal. The receiving circuit samples received data according to the sampling clock signal, the phase-early sampling clock signal and the phase-late sampling clock signal to generate a sample result. The training circuit controls the clock generating circuit to generate the sampling clock signal and the corresponding phase-early sampling clock signal and phase-late sampling clock signal that have different phases in a plurality of different time intervals, respectively, to cause the receiving circuit to generate a plurality of sample results. The training circuit further determines a sampling phase of the sampling clock signal according to the sample results.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: March 24, 2020
    Assignee: MEDIATEK INC.
    Inventors: Ming-Han Weng, Wei-Yung Wang, Chih-Hung Lin, Jyun Yang Shih, Chun-Chia Chen
  • Publication number: 20200078304
    Abstract: The present invention generally relates to reducing the mucoadhesive properties of a particle. In some embodiments, the particle is coated with and/or associated with a (poly(ethylene glycol))-(poly(propylene oxide))-(poly(ethylene glycol)) triblock copolymer. Methods for preparing inventive particles using a poly(ethylene glycol)-vitamin E conjugate as a surfactant are also provided. In some embodiments, methods are provided comprising administering to a subject a composition of particles of the present invention. Such particles with reduced mucoadhesive properties are useful in delivering agents to mucosal tissues such as oral, ophthalmic, gastrointestinal, nasal, respiratory, and genital mucosal tissues.
    Type: Application
    Filed: July 12, 2019
    Publication date: March 12, 2020
    Inventors: Samuel K. Lai, Ming Yang, Ying-Ying Wang, Olcay Mert, Laura Ensign, Justin Hanes, Jie Fu
  • Patent number: 10504515
    Abstract: A voice control device includes a microphone module, a voice encoding module, a display and a processing unit. The voice encoding module is electrically connected to the microphone module. The processing unit is electrically connected to the voice encoding module and the display. The microphone module receives a voice signal and transmits the received voice signal to the voice encoding module. One of the voice encoding module and the processing unit analyzes and processes the voice signal to determine a sound source direction of the voice signal and obtains response information according to the voice signal. The processing unit controls the display to rotate to the sound source direction and transmits the response information to the display for displaying the response information.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: December 10, 2019
    Assignee: Chiun Mai Communication Systems, Inc.
    Inventors: Yu-Yang Chih, Ming-Chun Ho, Ming-Fu Tsai, Cheng-Ping Liu, Fu-Bin Wang, Shih-Lun Lin
  • Publication number: 20190291401
    Abstract: A method for bonding a first component to a second component includes placing the first and second components in a cavity. Each of the first and second components has a bonding portion, and the bonding portion of the first component faces the bonding portion of the second component. A supercritical fluid is then introduced into the cavity with a temperature of 40-400° C. and a pressure of 1,500-100,000 psi, and a pressure of 4-100,000 psi is applied on both the first and second components, assuring the bonding portion of the first component bond to the bonding portion of the second component. Moreover, a method for separating a first component from a second component includes placing a composite in a cavity. The composite includes the first component, the second component and a connecting layer by which the first component joins to the second component. The supercritical is then introduced into the cavity.
    Type: Application
    Filed: June 25, 2018
    Publication date: September 26, 2019
    Inventors: Ting-Chang Chang, Chih-Cheng Shih, Ming-Hui Wang, Wen-Chung Chen, Chih-Yang Lin
  • Publication number: 20190277850
    Abstract: The present invention provides a method of evaluating drug resistance in hormone therapy including the following steps. Firstly, a primary level of TRBP in a subject is measured, and an effective amount of tamoxifen, an active form of tamoxifen or an analogous of tamoxifen is provided to the subject. Then, a level of TRBP in the subject is measured after providing tamoxifen, the active form of tamoxifen or the analogous of tamoxifen. Finally, a level change of TRBP in the subject is discriminated to determine a tamoxifen resistance.
    Type: Application
    Filed: December 4, 2018
    Publication date: September 12, 2019
    Inventors: Pai-Sheng Chen, Jie-Ning Li, Yao-Lung Kuo, Ming-Yang Wang
  • Patent number: 10362551
    Abstract: The present invention discloses a calibration method for parallel multi-channel wireless channel measurement and a calibration system thereof. The transmitting end and the receiving end are disconnected, and are respectively connected to the calibration receiving channel and the calibration transmitting channel, and the calibration receiving channel/calibration transmitting channel cooperates with a measurement channel in air interface measurement, to calibrate a channel response characteristic of the transmitting end and the receiving end. By means of the present invention, a current channel response characteristic between multiple channels can be online supervised in real time, so as to ensure that a measurement error because of an impact of mutual interference between multiple channels can be avoided in the channel measurement process.
    Type: Grant
    Filed: August 6, 2017
    Date of Patent: July 23, 2019
    Assignee: SHANGHAI RESEARCH CENTER FOR WIRELESS COMMUNICATIONS
    Inventors: Zhong-fei Cai, Yun-song Gui, Hao-wen Wang, Ming-tuo Zhou, Yang Yang, Hai-feng Wang
  • Publication number: 20190190789
    Abstract: The present invention discloses a computing capability description method for fog computing and a computing capability interaction method for fog computing, and further discloses a node device for fog computing. In the present invention, key parameters affecting a computing capability are further explored, and therefore, a computing capability of a node can be described more accurately. After these key parameters are obtained, a computing type and a scale of data that are suitable for being processed by the node can be better determined, and a delay and costs that are needed by the node to execute a computing task can be better pre-estimated, so as to further assist in computing task allocation between nodes.
    Type: Application
    Filed: December 27, 2017
    Publication date: June 20, 2019
    Inventors: Meng-ying ZHANG, Ming-tuo Zhou, Yang Yang, Hai-feng Wang
  • Patent number: 9449138
    Abstract: A system for emulating a circuit design is presented. The system includes a host workstation coupled by an emulation interface to a field programmable gate array (FPGA) configured to emulate and verify the circuit design when the host workstation is invoked to verify the circuit design. The emulation interface is configured to provide timing and control information for at least the verify. The system further includes a non-transitory computer readable storage medium including instructions, which when executed cause a computer to compile a portion of the circuit design and an associated verification module adapted to configure the FPGA. A compilation is performed in accordance with a description file.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: September 20, 2016
    Assignee: Synopsys, Inc.
    Inventors: Yingtsai Chang, Sweyyan Shei, Hung-Chun Chiu, Meng-Chyi Lin, Hwa Mao, Ming-Yang Wang, Yu-Chin Hsu
  • Patent number: 8949752
    Abstract: An emulation system integrates multiple custom prototyping boards for emulating a circuit design. A first custom prototyping board including at least one FPGA and an interface connected to a first set of wires coupling to the at least one FPGA. A second custom prototyping board includes at least one second FPGA and an interface connected to a second set of wires coupling to the at least second FPGA. An adaptor board connects to the first custom prototyping board and the second custom prototyping board through the first interface and the second interface. The adapter board controls emulation of the circuit design and controls communication through the partitioned circuit using at least one of the first set of wires and at least one the second set of wires.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: February 3, 2015
    Assignee: Synopsys, Inc.
    Inventors: Ming-Yang Wang, Sweyyan Shei
  • Publication number: 20140351777
    Abstract: A system for emulating a circuit design is presented. The system includes a host workstation coupled by an emulation interface to a field programmable gate array (FPGA) configured to emulate and verify the circuit design when the host workstation is invoked to verify the circuit design. The emulation interface is configured to provide timing and control information for at least the verify. The system further includes computer readable storage medium including instructions, which when executed cause a computer to compile a portion of the circuit design and an associated verification module adapted to configure the FPGA. The compilation is in accordance with a description file.
    Type: Application
    Filed: August 5, 2014
    Publication date: November 27, 2014
    Inventors: Yingtsai Chang, Sweyyan Shei, Hung-Chun Chiu, Meng-Chyi Lin, Hwa Mao, Ming-Yang Wang, Yu-Chin Hsu
  • Patent number: 8852150
    Abstract: A DC-AC frequency converter type nose cleaner includes an electromagnetic pump, a container storing a cleaning solution, a nose-washing tool and a frequency converter circuit driving the electromagnetic pump. The frequency converter circuit at least includes an oscillator circuit, a bistable circuit and a push-pull circuit. The swing speed, the swing frequency and the swing amplitude of the swing arms vary with the change of the oscillation frequency of the oscillator circuit. The DC-AC frequency converter type nose cleaner can change the pressure and the flow generated by the electromagnetic pump so as to satisfy the requirement of the discharge pressure and flow of the nose cleaner so as to overcome the defect of the discharge pressure of the conventional nose cleaner that is too big to hurt the user.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: October 7, 2014
    Inventor: Ming Yang Wang
  • Patent number: 8839179
    Abstract: A test system for testing prototype designs includes a host workstation, multiple interface devices, and multiple prototype boards. The prototype boards include programmable devices which implement one or more partitions of a user design and an associated verification modules. The verification modules probe signals of the partitions and transmit the probed signals to the interface devices. The verification modules can also transmit output signals generated by one or more partitions on the prototype boards to the host workstation via the interface devices, and transmit input signals, which are received from the host workstation via the interface devices, to one or more partitions on the prototype boards.
    Type: Grant
    Filed: April 3, 2013
    Date of Patent: September 16, 2014
    Assignee: Synopsys Taiwan Co., Ltd.
    Inventors: Yingtsai Chang, Sweyyan Shei, Hung-Chun Chiu, Meng-Chyi Lin, Hwa Mao, Ming Yang Wang, Yuchin Hsu
  • Publication number: 20140157215
    Abstract: An emulation system integrates multiple custom prototyping boards for emulating a circuit design. A first custom prototyping board including at least one FPGA and an interface connected to a first set of wires coupling to the at least one FPGA. A second custom prototyping board includes at least one second FPGA and an interface connected to a second set of wires coupling to the at least second FPGA. An adaptor board connects to the first custom prototyping board and the second custom prototyping board through the first interface and the second interface. The adapter board controls emulation of the circuit design and controls communication through the partitioned circuit using at least one of the first set of wires and at least one the second set of wires.
    Type: Application
    Filed: November 25, 2013
    Publication date: June 5, 2014
    Applicant: Synopsys, Inc.
    Inventors: Ming-Yang Wang, Sweyyan Shei
  • Patent number: 8732650
    Abstract: A method for emulating a circuit design includes receiving, at an emulation interface, signal values associated with probed signals from a verification module of a custom prototype board which can be described by at least one board description file and can comprise at least one field programmable gate array for emulating the circuit design. The method can also include processing, the probed signal values associated with a portion of the circuit design being emulated, the emulation interface being capable of being configured to provide timing and control information to at least the verification module, and can comprise a controller and a memory device, with the controller being capable of being configured to receive the probed signal values. The method can further include storing the processed information and transmitting it to the host workstation.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: May 20, 2014
    Assignees: Synopsys Taiwan Co., Ltd., Synopsys, Inc.
    Inventors: Yingtsai Chang, Sweyyan Shei, Hung Chun Chiu, Hwa Mao, Ming Yang Wang, Yuchin Hsu
  • Patent number: D884221
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: May 12, 2020
    Assignee: JIAXING SUPER LIGHTING ELECTRIC APPLIANCE CO., LTD
    Inventors: Ming-Bin Wang, Tao Jiang, Da-Hong Chen, Tian-Yang Xi