Patents by Inventor Ming Yao

Ming Yao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145610
    Abstract: A tunnel oxide layer, an N-type bifacial crystalline silicon solar cell and a method for manufacturing the same are provided. The method for manufacturing the tunnel oxide layer includes forming excess -OH on a back side of a silicon wafer, and depositing the tunnel oxide layer on the back side of the silicon wafer by a Plasma Enhanced Atomic Layer Deposition method. The method for manufacturing the N-type bifacial crystalline silicon solar cell can include following steps: performing cleaning, texturing, boron diffusing, and alkaline polishing on an N-type silicon wafer, sequentially forming a P-type doped layer, a passivation layer, and an anti-reflection layer on a front side of the alkaline-polished N-type silicon wafer, and forming a tunnel oxide layer on a back side of the alkaline-polished N-type silicon wafer, followed by forming an N-type doped polysilicon layer, and after annealing, forming an anti-reflection layer.
    Type: Application
    Filed: July 27, 2022
    Publication date: May 2, 2024
    Inventors: Ming ZHANG, Xiajie MENG, Wenzhou XU, Hao CHEN, Mingzhang DENG, Guoqiang XING, Qian YAO
  • Publication number: 20240142301
    Abstract: The present disclosure provides a sensing circuit, including a photo-sensing component, a first transistor, and a temperature-sensing component. The photo-sensing component is configured to receive a light and transmit a first current according to an intensity of the light. A gate terminal of the first transistor is configured to receive a first control circuit. The photo-sensing component and the first transistor are coupled in series between first and second nodes. The temperature-sensing component is coupled between the first and second nodes and is configured to generate a second current according to a temperature. The temperature-sensing component includes a channel structure, a first gate, a second gate, and a light-shielding structure. The channel structure is configured to transmit the second current.
    Type: Application
    Filed: December 14, 2022
    Publication date: May 2, 2024
    Inventors: Ming-Yao CHEN, Chang-Hung LI, Shin-Shueh CHEN, Jui-Chi LO
  • Patent number: 11972545
    Abstract: The present disclosure provides an apparatus and method of guided neural network model for image processing. An apparatus may comprise a guidance map generator, a synthesis network and an accelerator. The guidance map generator may receive a first image as a content image and a second image as a style image, and generate a first plurality of guidance maps and a second plurality of guidance maps, respectively from the first image and the second image. The synthesis network may synthesize the first plurality of guidance maps and the second plurality of guidance maps to determine guidance information. The accelerator may generate an output image by applying the style of the second image to the first image based on the guidance information.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: April 30, 2024
    Assignee: INTEL CORPORATION
    Inventors: Anbang Yao, Ming Lu, Yikai Wang, Shandong Wang, Yurong Chen, Sungye Kim, Attila Tamas Afra
  • Patent number: 11971298
    Abstract: The present disclosure provides a sensing circuit, including a photo-sensing component, a first transistor, and a temperature-sensing component. The photo-sensing component is configured to receive a light and transmit a first current according to an intensity of the light. A gate terminal of the first transistor is configured to receive a first control circuit. The photo-sensing component and the first transistor are coupled in series between first and second nodes. The temperature-sensing component is coupled between the first and second nodes and is configured to generate a second current according to a temperature. The temperature-sensing component includes a channel structure, a first gate, a second gate, and a light-shielding structure. The channel structure is configured to transmit the second current.
    Type: Grant
    Filed: December 14, 2022
    Date of Patent: April 30, 2024
    Assignee: AUO CORPORATION
    Inventors: Ming-Yao Chen, Chang-Hung Li, Shin-Shueh Chen, Jui-Chi Lo
  • Patent number: 11969844
    Abstract: A method for detecting and compensating CNC tools being implemented in an electronic device, receives from a detector first parameters and second parameters in respect of a first tool. Such first parameters include at least one of service life, blade break information, and blade chipping information of the first tool, and such second parameters include at least one of length extension information, length wear information, radial wear information, and blade thickness wear information of the first tool. Based on the first parameters, instructions to process the workpiece are transmitted or not. Upon receiving the second parameters, instructions to adjust operation of the first tool are transmitted, to compensate for deterioration in normal use.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: April 30, 2024
    Assignee: Fulian Yuzhan Precision Technology Co., Ltd
    Inventors: Hsing-Chih Hsu, Zhao-Yao Yi, Lei Zhu, Chang-Li Zhang, Er-Yang Ma, Chih-Sheng Lin, Feng Xie, Ming-Tao Luo
  • Publication number: 20240131655
    Abstract: The present disclosure provides a chemical mechanical polishing device including a retaining ring and a wafer carrier and a polishing method. The retaining ring is configured on a polishing pad and includes an inner sidewall defining an opening and an outer sidewall opposite to the inner sidewall. The wafer carrier is configured on the polishing pad and is capable of placing a wafer disposed thereon into the opening and facing the polishing pad. The retaining ring has a notch at the corner adjacent to the wafer and the polishing pad.
    Type: Application
    Filed: November 28, 2022
    Publication date: April 25, 2024
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Ming-Hsiang Chen, Shih-Ci Yen, Kai-Yao Shih
  • Patent number: 11965412
    Abstract: A quantitative evaluation method for integrity and damage evolution of a cement sheath in an oil-gas well is provided based on a fractal theory, an image processing technology, structural features and failure mechanisms of a casing-cement sheath-formation combination. The method uses correlations among fractal dimensions of casing-cement sheath interface morphology, cement sheath microscopic pore morphology, particle morphology of an initial blank group, and macroscopic mechanical properties including a radial cementing strength of the cement sheath interface, a tensile strength, and a compressive strength to quantitatively evaluate the integrity of the cement sheath of the blank group.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: April 23, 2024
    Assignee: SOUTHWEST PETROLEUM UNIVERSITY
    Inventors: Kuanhai Deng, Niantao Zhou, Yuanhua Lin, Mingyuan Yao, Ming Zhang, Deqiang Yi, Pengfei Xie, Yang Peng
  • Publication number: 20240130085
    Abstract: A cooling system includes a housing including a base portion with sides and a bottom surface that define a cavity and a cover portion to enclose the base portion and including cooling members attached thereto. A shield is arranged in the cavity. A vertical member is arranged below the shield to define a first fluid chamber between one side of the vertical member and one side of the base portion and a second fluid chamber between an opposite side of the vertical member and another side of the base portion. The electronic components are arranged in the second fluid chamber. Cooling fluid is arranged in the cavity and has a fluid level below at least a portion of the shield. The housing is mounted at an inclined angle relative to horizontal or the housing is mounted parallel to horizontal and the shield is mounted at the inclined angle.
    Type: Application
    Filed: March 28, 2023
    Publication date: April 18, 2024
    Inventors: Ming LIU, Jian Yao, Chengwu Duan, Chih-hung Yen, Anil K. Sachdev
  • Publication number: 20240128148
    Abstract: A method includes attaching a package component to a package substrate, the package component includes: an interposer disposed over the package substrate; a first die disposed along the interposer; and a second die disposed along the interposer, the second die being laterally adjacent the first die; attaching a first thermal interface material to the first die, the first thermal interface material being composed of a first material; attaching a second thermal interface material to the second die, the second thermal interface material being composed of a second material different from the first material; and attaching a lid assembly to the package substrate, the lid assembly being further attached to the first thermal interface material and the second thermal interface material.
    Type: Application
    Filed: January 6, 2023
    Publication date: April 18, 2024
    Inventors: Chang-Jung Hsueh, Po-Yao Lin, Hui-Min Huang, Ming-Da Cheng, Kathy Yan
  • Publication number: 20240127408
    Abstract: Embodiments are generally directed to an adaptive deformable kernel prediction network for image de-noising. An embodiment of a method for de-noising an image by a convolutional neural network implemented on a compute engine, the image including a plurality of pixels, the method comprising: for each of the plurality of pixels of the image, generating a convolutional kernel having a plurality of kernel values for the pixel; generating a plurality of offsets for the pixel respectively corresponding to the plurality of kernel values, each of the plurality of offsets to indicate a deviation from a pixel position of the pixel; determining a plurality of deviated pixel positions based on the pixel position of the pixel and the plurality of offsets; and filtering the pixel with the convolutional kernel and pixel values of the plurality of deviated pixel positions to obtain a de-noised pixel.
    Type: Application
    Filed: November 20, 2023
    Publication date: April 18, 2024
    Applicant: Intel Corporation
    Inventors: Anbang Yao, Ming Lu, Yikai Wang, Xiaoming Chen, Junjie Huang, Tao Lv, Yuanke Luo, Yi Yang, Feng Chen, Zhiming Wang, Zhiqiao Zheng, Shandong Wang
  • Publication number: 20240118660
    Abstract: Embodiments of this application provide example holographic recording media, holographic polymer materials, methods for preparing holographic polymer materials, and display devices. An example holographic recording medium includes a first-order crosslinked network, a photoinitiator, and a second-order monomer. The first-order crosslinked network provides a mechanical support for the holographic recording medium. The second-order monomer includes a monomer with a free radical reactivity. The photoinitiator is used to initiate polymerization of the second-order monomer. The holographic recording medium includes at least one of an ester group (I), a urethane group (II), a carbamido group (III), an allophanate group (IV), or an amide group (V). Groups linked to the ester group (I), the urethane group (II), the carbamido group (III), the allophanate group (IV), and the amide group (V) are separately selected from at least one of the following: alkyl, alkoxy, alkenyl, or aryl.
    Type: Application
    Filed: November 22, 2023
    Publication date: April 11, 2024
    Inventors: Haiyan PENG, Shaoqin XU, Xiaolin XIE, Xingping ZHOU, Ming YAO, Botong QIU
  • Publication number: 20240096705
    Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Yu Kao, Chen-Yui Yang, Hsien-Chung Huang, Chao-Cheng Chen, Shih-Yao Lin, Chih-Chung Chiu, Chih-Han Lin, Chen-Ping Chen, Ke-Chia Tseng, Ming-Ching Chang
  • Publication number: 20240096822
    Abstract: A package structure is provided. The package structure includes a first conductive pad in a first insulating layer, a conductive via in a second insulating layer directly under the first conductive pad, and a first under bump metallurgy structure directly under the first conductive via. In a first horizontal direction, the conductive via is narrower than the first under bump metallurgy structure, and the first under bump metallurgy structure is narrower than the first conductive pad.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Chia-Kuei HSU, Ming-Chih YEW, Shu-Shen YEH, Che-Chia YANG, Po-Yao LIN, Shin-Puu JENG
  • Publication number: 20240096893
    Abstract: A semiconductor device includes a substrate. The semiconductor device includes a fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate structure that straddles the fin and extends along a second direction perpendicular to the first direction. The semiconductor device includes a first source/drain structure coupled to a first end of the fin along the first direction. The gate structure includes a first portion protruding toward the first source/drain structure along the first direction. A tip edge of the first protruded portion is vertically above a bottom surface of the gate structure.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Shih-Yao Lin, Chao-Cheng Chen, Chih-Han Lin, Ming-Ching Chang, Wei-Liang Lu, Kuei-Yu Kao
  • Publication number: 20240083201
    Abstract: A vehicle tire cloud computing management system and an application method thereof are provided. A vehicle tire cloud computing management system is formed by combining a vehicle tire management device including tire sensors, a setting tool, and radio frequency identification (RFID) tags with a cloud server, and a car computer. By using the tire sensors to detect tire-related data, and then by outputting the tire-related data to the setting tool, the cloud server, or the car computer for data computation, result judging and/or data storage, so that the function of the tire sensors is more focused on detecting tire conditions, and power consumption of the tire sensors is reduced, while the setting tool, the cloud server, and the car computer are used efficiently to perform computation, management, and application for data related to the tire sensors.
    Type: Application
    Filed: June 11, 2023
    Publication date: March 14, 2024
    Applicant: ORANGE ELECTRONIC CO., LTD.
    Inventors: Chin-yao HSU, Jian-zhi WANG, Ming-yung HUANG
  • Publication number: 20240088095
    Abstract: A method for forming a chip package structure. The method includes bonding first connectors over a front surface of a semiconductor wafer. The method also includes dicing the semiconductor wafer from a rear surface of the semiconductor wafer to form semiconductor dies and mounting first and second semiconductor dies in the semiconductor dies over a top surface of the interposer substrate. The method further forming an encapsulating layer over the top surface of the interposer substrate to cover the first semiconductor die and the second semiconductor die. A first sidewall of the first semiconductor die faces a second sidewall of the second semiconductor die, and upper portions of the first sidewall and the second sidewall have a tapered contour, to define a top die-to-die distance and a bottom die-to-die distance that is less than the top die-to-die distance.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 14, 2024
    Inventors: Chin-Hua WANG, Shin-Puu JENG, Po-Yao LIN, Po-Chen LAI, Shu-Shen YEH, Ming-Chih YEW, Yu-Sheng LIN
  • Publication number: 20240077626
    Abstract: A signal processing system and method for a radiation detector based on a metal oxide semiconductor (MOS) transistor are disclosed. The signal processing system includes a power supply generation module, an analog signal processing module, and a digital signal acquiring-processing module. The power supply generation module provides a novel power supply method, and converts a positive high voltage power supply into a negative high voltage power supply to supply power to a last dynode of a photomultiplier tube (PMT). The analog signal processing module converts a negative current pulse signal into a voltage difference signal. The digital signal acquiring-processing module acquires a signal of the analog signal processing module, and converts the signal into a digital signal for identification.
    Type: Application
    Filed: January 4, 2023
    Publication date: March 7, 2024
    Inventors: Qiang Liu, Zhenhua Lin, Jinhan Wang, Kunliang Yao, Yudong Luo, Sheng Wu, Yongjie Wang, Jianzheng Gao, Ming Cui
  • Patent number: 11923870
    Abstract: A method for constructing an n-qubit fault tolerant encode for any k-qubit quantum gate M, in any given quantum code [n, k, C], comprising: choosing a number n?k of independent spinors Sr from the first stabilizer C and a first ordered set SC consists of the independent spinors Sr; choosing a number n?k of independent spinors ?r from a second stabilizer ? in the intrinsic coordinate and a second ordered set ?r consists of the independent spinors ?r consist; implementing an encoding Qen, wherein the encoding Qen converts the first ordered set SC to the second ordered set S?, wherein the encoding Qen is a sequential product provided by sequential operations of a number n?k of unitary operators Qr; wherein each of the unitary operator Qr is composed of a single s-rotation or a product of two s-rotations; and wherein the encoding Qen converts and maps the rth independent spinor Sr in the first ordered set SC to the rth independent spinor ?r in the second ordered set S? correspondingly; a fault tolerant action Û i
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: March 5, 2024
    Assignee: National Applied Research Laboratories
    Inventors: Zheng-Yao Su, Ming-Chung Tsai
  • Publication number: 20240021650
    Abstract: A semiconductor die includes a semiconductor device fabricated in a substrate. The substrate has a front side, a back side, and an inclined sidewall extending from the back side to the front side. A contact pad is connected to the semiconductor device. The contact pad is embedded in an inter dielectric layer (IDL) disposed in the front side. The contact pad has a contact pad edge with a surface aligned along the inclined sidewall. A redistribution layer (RDL) is disposed on the inclined sidewall. The RDL is physically and electrically connected to the contact pad directly through the surface of the contact pad edge aligned along the inclined sidewall.
    Type: Application
    Filed: July 11, 2023
    Publication date: January 18, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Ming-Yao CHEN, Chien-Wei CHANG
  • Publication number: 20240016327
    Abstract: The present invention discloses a decorated tree bracket base. A locking seat is installed on an upper sleeve, the locking seat has a sleeve structure, and an inserting through hole which is the same as a center hole of the supporting tube shaft is formed in the locking seat; a plurality of elastic clamping strips are formed on the lower hole edge of the inserting through hole, and the upper end of each elastic clamping strip is connected with the lower hole edge of the inserting through hole by a single point. An elastic clamping structure can not only realize the effect of fixing the trunk of the decorated tree, but also provide a simpler and more efficient installation method and a low installation difficulty, which is more in line with the current market demand.
    Type: Application
    Filed: July 25, 2023
    Publication date: January 18, 2024
    Inventor: MING-YAO CHIANG