Patents by Inventor Ming-Yen Chuang
Ming-Yen Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240105249Abstract: An integrated circuit includes an array of word lines, and an array of memory cells configured to receive selection signals from the array of word lines. Each memory cell in the array of memory cells is connected to one or more data lines in a set of data lines. The integrated circuit also includes a read-write driver which is connected to the set of data lines and is configured to receive a flip-refresh control signal. The read-write driver has a catch circuit configured to store a first bit value related to a stored bit value in a selected memory cell. The read-write driver is configured to store into the selected memory cell a second bit value which is a bit inversion of the stored bit value.Type: ApplicationFiled: January 27, 2023Publication date: March 28, 2024Inventors: Ming-Yen CHUANG, Katherine H. CHIANG
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Patent number: 11935966Abstract: A transistor device includes a first source/drain region and a second source/drain region spaced apart from each other; a channel layer electrically connected to the first and second source/drain regions; a gate insulator layer; a gate electrode isolated from the channel layer by the gate insulator layer; and a UV-attenuating layer disposed on the channel layer to protect the channel layer from characteristic degradation caused by UV light.Type: GrantFiled: April 28, 2021Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Katherine H. Chiang, Neil Quinn Murray, Ming-Yen Chuang, Chung-Te Lin
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Patent number: 11895832Abstract: A memory integrated circuit is provided. The memory integrated circuit includes a first memory array, a second memory array and a driving circuit. The first and second memory arrays are laterally spaced apart, and respectively include: memory cells, each including an access transistor and a storage capacitor coupled to the access transistor; bit lines, respectively coupled to a row of the memory cells; and word lines, respectively coupled to a column of the memory cells. The driving circuit is disposed below the first and second memory arrays, and includes sense amplifiers. Each of the bit lines in the first memory array and one of the bit lines in the second memory array are routed to input lines of one of the sense amplifiers.Type: GrantFiled: August 6, 2021Date of Patent: February 6, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yun-Feng Kao, Ming-Yen Chuang, Katherine H. Chiang, Chia-En Huang
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Patent number: 11839071Abstract: A plurality of vertical stacks may be formed over a substrate. Each of the vertical stacks includes, from bottom to top, a bottom electrode, a dielectric pillar, and a top electrode. A continuous active layer may be formed over the plurality of vertical stacks. A gate dielectric layer may be formed over the continuous active layer. The continuous active layer and the gate dielectric layer may be patterned into a plurality of active layers and a plurality of gate dielectrics. Each of the plurality of active layers laterally surrounds a respective one of the vertical stacks that are arranged along a first horizontal direction, and each of the plurality of gate dielectrics laterally surrounds a respective one of the active layers. Gate electrodes may be formed over the plurality of gate dielectrics.Type: GrantFiled: July 22, 2021Date of Patent: December 5, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Ming-Yen Chuang, Katherine H. Chiang
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Publication number: 20230378349Abstract: A semiconductor structure includes vertical stacks located over a substrate, wherein each of the vertical stacks includes from bottom to top, a bottom electrode, a dielectric pillar structure including a lateral opening therethrough, and a top electrode; layer stacks located over the vertical stacks, wherein each of the layer stacks includes an active layer and an outer gate dielectric and laterally surrounds a respective one of the vertical stacks; inner gate electrodes passing through a respective subset of the lateral openings in a respective row of vertical stacks that are arranged along a first horizontal direction; and outer gate electrodes laterally extending along the first horizontal direction and laterally surrounding a respective row of layer stacks.Type: ApplicationFiled: August 7, 2023Publication date: November 23, 2023Inventors: Ming-Yen CHUANG, Katherine H. CHIANG, Yun-Feng KAO
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Publication number: 20230380181Abstract: A plurality of vertical stacks may be formed over a substrate. Each of the vertical stacks includes, from bottom to top, a bottom electrode, a dielectric pillar, and a top electrode. A continuous active layer may be formed over the plurality of vertical stacks. A gate dielectric layer may be formed over the continuous active layer. The continuous active layer and the gate dielectric layer may be patterned into a plurality of active layers and a plurality of gate dielectrics. Each of the plurality of active layers laterally surrounds a respective one of the vertical stacks that are arranged along a first horizontal direction, and each of the plurality of gate dielectrics laterally surrounds a respective one of the active layers. Gate electrodes may be formed over the plurality of gate dielectrics.Type: ApplicationFiled: August 7, 2023Publication date: November 23, 2023Inventors: Ming-Yen CHUANG, Katherine H. CHIANG
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Publication number: 20230361216Abstract: A semiconductor device includes a substrate and a transistor structure disposed on the substrate. The transistor structure includes a channel region and a source/drain electrode disposed on the channel region. The channel region includes a lower channel portion and a plurality of upper channel portions protruding from the lower channel portion into the source/drain electrode to form an uneven interface between the channel region and the source/drain electrode.Type: ApplicationFiled: May 5, 2022Publication date: November 9, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Yen CHUANG, Katherine H. CHIANG
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Patent number: 11695039Abstract: Provided are a semiconductor device and method of forming the same. The semiconductor device includes active components and a first barrier pattern. The active components are on a substrate. Each of the active components includes base insulation patterns on the substrate, gate electrodes on the substrate and spaced apart from each other with the base insulation patterns interposed therebetween, a gate dielectric layer on the gate electrodes and the base insulation patterns, a channel pattern on the gate dielectric layer, source electrodes on the channel pattern and spaced apart from each other, a drain electrode on the channel pattern and between the source electrodes, and second insulation patterns between the source electrodes and the drain electrode. The first barrier pattern disposed on the gate dielectric layer surrounds the channel patterns, the source electrodes, the drain electrodes, and the second insulation patterns of each of the active components.Type: GrantFiled: July 30, 2021Date of Patent: July 4, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hao Huang, Gao-Ming Wu, Yun-Feng Kao, Ming-Yen Chuang, Katherine H. Chiang
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Publication number: 20230058626Abstract: A transistor includes a gate electrode, a gate dielectric layer covering the gate electrode, an active layer covering the gate dielectric layer and including a first metal oxide material, and source/drain electrodes disposed on the active layer and made of a second metal oxide material with an electron concentration of at least about 1018 cm?3. A semiconductor structure and a manufacturing method are also provided.Type: ApplicationFiled: August 19, 2021Publication date: February 23, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Yen Chuang, Chang-Lin Yang, Katherine H. CHIANG, Mauricio MANFRINI
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Publication number: 20230041409Abstract: A memory integrated circuit is provided. The memory integrated circuit includes a first memory array, a second memory array and a driving circuit. The first and second memory arrays are laterally spaced apart, and respectively include: memory cells, each including an access transistor and a storage capacitor coupled to the access transistor; bit lines, respectively coupled to a row of the memory cells; and word lines, respectively coupled to a column of the memory cells. The driving circuit is disposed below the first and second memory arrays, and includes sense amplifiers. Each of the bit lines in the first memory array and one of the bit lines in the second memory array are routed to input lines of one of the sense amplifiers.Type: ApplicationFiled: August 6, 2021Publication date: February 9, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yun-Feng Kao, Ming-Yen Chuang, Katherine H. CHIANG, Chia-En Huang
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Patent number: 11574909Abstract: A semiconductor device includes a transistor, a bit line and a bit-line via structure. The transistor is located in a transistor layer, and has a source contact and a drain contact. The bit line is electrically connected to one of the source contact and the drain contact. The bit-line via structure is located in the transistor layer, and electrically interconnects the bit line and a periphery device.Type: GrantFiled: May 27, 2021Date of Patent: February 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Yen Chuang, Katherine H. Chiang
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Publication number: 20230032528Abstract: Provided are a semiconductor device and method of forming the same. The semiconductor device includes active components and a first barrier pattern. The active components are on a substrate. Each of the active components includes base insulation patterns on the substrate, gate electrodes on the substrate and spaced apart from each other with the base insulation patterns interposed therebetween, a gate dielectric layer on the gate electrodes and the base insulation patterns, a channel pattern on the gate dielectric layer, source electrodes on the channel pattern and spaced apart from each other, a drain electrode on the channel pattern and between the source electrodes, and second insulation patterns between the source electrodes and the drain electrode. The first barrier pattern disposed on the gate dielectric layer surrounds the channel patterns, the source electrodes, the drain electrodes, and the second insulation patterns of each of the active components.Type: ApplicationFiled: July 30, 2021Publication date: February 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hao Huang, Gao-Ming Wu, Yun-Feng Kao, Ming-Yen Chuang, Katherine H. Chiang
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Publication number: 20230025820Abstract: A plurality of vertical stacks may be formed over a substrate. Each of the vertical stacks includes, from bottom to top, a bottom electrode, a dielectric pillar, and a top electrode. A continuous active layer may be formed over the plurality of vertical stacks. A gate dielectric layer may be formed over the continuous active layer. The continuous active layer and the gate dielectric layer may be patterned into a plurality of active layers and a plurality of gate dielectrics. Each of the plurality of active layers laterally surrounds a respective one of the vertical stacks that are arranged along a first horizontal direction, and each of the plurality of gate dielectrics laterally surrounds a respective one of the active layers. Gate electrodes may be formed over the plurality of gate dielectrics.Type: ApplicationFiled: July 22, 2021Publication date: January 26, 2023Inventors: Ming-Yen CHUANG, Katherine H. CHIANG
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Publication number: 20230019688Abstract: A disclosed capacitor structure includes a support structure including a plurality of elongated structures each extending along a longitudinal direction, a transverse direction, and a vertical direction. The plurality of elongated structures includes an alternating stack of first dielectric layers and second dielectric layers, a bottom electrode formed over the support structure, a third dielectric layer formed over the bottom electrode, and a top electrode formed over the third dielectric layer. Each of the first dielectric layers includes a first width along the transverse direction and each of the second dielectric layers includes a second width along the transverse direction. In various embodiments, the first width may be less than the second width such that each of the plurality of elongated structures include walls including a corrugated width profile as a function of distance along the vertical direction. The capacitor structure may be formed in a BEOL process.Type: ApplicationFiled: March 15, 2022Publication date: January 19, 2023Inventors: Yun-Feng Kao, Ming-Yen Chuang, Katherine H. Chiang, Chien-Hao HUANG
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Publication number: 20230018869Abstract: A semiconductor die includes semiconductor substrate and interconnection structure. Interconnection structure includes first conductive lines, first conductive patterns, first pillar stacks, second pillar stacks, gate patterns. First conductive lines extend parallel to each other in first direction and are embedded in interlayer dielectric layer. First conductive patterns are disposed in row along first direction and are embedded in interlayer dielectric layer beside first conductive lines. First pillar stacks include first pairs of metallic blocks separated by first dielectric material blocks. Second pillar stacks include second pairs of metallic blocks separated by second dielectric material blocks. Each second pillar stack is electrically connected to respective first conductive pattern. Gate patterns extend substantially perpendicular to first conductive lines. Each gate pattern directly contacts one respective second pillar stack and extends over a group of first pillar stacks.Type: ApplicationFiled: July 15, 2021Publication date: January 19, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Yen Chuang, Katherine H. CHIANG
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Publication number: 20230008902Abstract: A semiconductor structure includes vertical stacks located over a substrate, wherein each of the vertical stacks includes from bottom to top, a bottom electrode, a dielectric pillar structure including a lateral opening therethrough, and a top electrode; layer stacks located over the vertical stacks, wherein each of the layer stacks includes an active layer and an outer gate dielectric and laterally surrounds a respective one of the vertical stacks; inner gate electrodes passing through a respective subset of the lateral openings in a respective row of vertical stacks that are arranged along a first horizontal direction; and outer gate electrodes laterally extending along the first horizontal direction and laterally surrounding a respective row of layer stacks.Type: ApplicationFiled: September 29, 2021Publication date: January 12, 2023Inventors: Ming-Yen CHUANG, Katherine H. CHIANG, Yun-Feng KAO
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Publication number: 20220384447Abstract: A semiconductor device includes a transistor, a bit line and a bit-line via structure. The transistor is located in a transistor layer, and has a source contact and a drain contact. The bit line is electrically connected to one of the source contact and the drain contact. The bit-line via structure is located in the transistor layer, and electrically interconnects the bit line and a periphery device.Type: ApplicationFiled: May 27, 2021Publication date: December 1, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Yen CHUANG, Katherine H. CHIANG
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Publication number: 20220367789Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip, the method includes forming a memory cell stack over a substrate. The memory cell stack comprises a tunnel barrier layer, a free layer over the tunnel barrier layer, a capping dielectric layer over the free layer, and a conductive capping layer on the capping dielectric layer. A conductive shunting structure is formed along outer sidewalls of the free layer, outer sidewalls of the capping dielectric layer, and outer sidewalls of the conductive capping layer. A bottommost point of the conductive shunting structure in contact with the free layer is disposed above a bottom surface of the free layer.Type: ApplicationFiled: July 27, 2022Publication date: November 17, 2022Inventors: Ming-Yen Chuang, Wenchin Lin
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Publication number: 20220359524Abstract: A semiconductor structure includes a two-dimensional array of unit cell structures overlying a substrate. Each unit cell structure includes an active layer, a gate dielectric underlying the active layer, two gate electrodes underlying the gate dielectric, and two source electrodes and a drain electrode overlying the active layer. Word lines underlie the active layers. Each unit cell structure includes portions of a respective set of four word lines, which includes two word lines that are electrically connected to two electrodes in the unit cell structure and two additional word lines that are electrically isolated from the two electrodes in the unit cell structure.Type: ApplicationFiled: September 24, 2021Publication date: November 10, 2022Inventors: Ming-Yen CHUANG, Chia LING, Katherine H. CHIANG, Chung-Te LIN
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Publication number: 20220352256Abstract: Semiconductor structures and methods of the forming the same are provided. A semiconductor structure according to the present disclosure includes a source feature and a drain feature, an active region between the source feature and the drain feature, a gate structure over the active region, a frontside interconnect structure disposed over the source feature, the drain feature, and the gate structure, a backside interconnect structure disposed below the source feature, the drain feature, and the gate structure, and a storage element disposed in the backside interconnect structure.Type: ApplicationFiled: August 16, 2021Publication date: November 3, 2022Inventors: Hsin-Wen Su, Jui-Lin Chen, Shih-Hao Lin, Ming-Yen Chuang, Chenchen Jacob Wang, Lien-Jung Hung, Ping-Wei Wang