Patents by Inventor Ming Yi Lim

Ming Yi Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for power management
    Patent number: 10248183
    Abstract: Particular embodiments described herein can offer a method for managing power for at least one processor that includes evaluating a plurality of ports associated with an electronic device; determining that a particular pin associated with at least one of the ports is not receiving a signal; disabling a squelch function associated with the electronic device; and gating power associated with a physical layer (PHY) of the electronic device.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventors: Jennifer Chin, Su Wei Lim, Poh Thiam Teoh, Ting Lok Song, Sun Zheng E, Say Cheong Gan, Sujea Lim, Ming Yi Lim
  • SYSTEM AND METHOD FOR POWER MANAGEMENT
    Publication number: 20170083079
    Abstract: Particular embodiments described herein can offer a method for managing power for at least one processor that includes evaluating a plurality of ports associated with an electronic device; determining that a particular pin associated with at least one of the ports is not receiving a signal; disabling a squelch function associated with the electronic device; and gating power associated with a physical layer (PHY) of the electronic device.
    Type: Application
    Filed: December 6, 2016
    Publication date: March 23, 2017
    Applicant: Intel Corporation
    Inventors: Jennifer Chin, Su Wei Lim, Poh Thiam Teoh, Ting Lok Song, Sun Zheng E, Say Cheong Gan, Sujea Lim, Ming Yi Lim
  • System and method for power management
    Patent number: 9513662
    Abstract: Particular embodiments described herein can offer a method for managing power for at least one processor that includes evaluating a plurality of ports associated with an electronic device; determining that a particular pin associated with at least one of the ports is not receiving a signal; disabling a squelch function associated with the electronic device; and gating power associated with a physical layer (PHY) of the electronic device.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: December 6, 2016
    Assignee: Intel Corporation
    Inventors: Jennifer Chin, Su Wei Lim, Poh Thiam Teoh, Ting Lok Song, Sun Zheng E, Say Cheong Gan, Sujea Lim, Ming Yi Lim
  • Method and apparatus for clock frequency ratio independent error logging
    Patent number: 9489008
    Abstract: A method and system for error logging that is independent of the clock frequency ratio in an I/O subsystem. In one embodiment of the invention, the I/O subsystem has an error logging mechanism with a fixed queue depth of two and is independent of the clock frequencies in the I/O subsystem. The I/O subsystem has two queue entries for storing or logging the uncorrectable errors. In one embodiment of the invention, the I/O subsystem has two queue entries for storing or logging the 128-bit TLP Header and the First Error Pointer (FEP) of the uncorrectable errors detected in the I/O subsystem.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: November 8, 2016
    Assignee: Intel Corporation
    Inventors: Ming Yi Lim, Su Wei Lim, Poh Thiam Teoh
  • SYSTEM AND METHOD FOR POWER MANAGEMENT
    Publication number: 20140195830
    Abstract: Particular embodiments described herein can offer a method for managing power for at least one processor that includes evaluating a plurality of ports associated with an electronic device; determining that a particular pin associated with at least one of the ports is not receiving a signal; disabling a squelch function associated with the electronic device; and gating power associated with a physical layer (PHY) of the electronic device.
    Type: Application
    Filed: January 4, 2013
    Publication date: July 10, 2014
    Inventors: Jennifer Chin, Su Wei Lim, Poh Thiam Teoh, Ting Lok Song, Sun Zheng E, Say Cheong Gan, Sujea Lim, Ming Yi Lim
  • METHOD AND APPARATUS FOR CLOCK FREQUENCY RATIO INDEPENDENT ERROR LOGGING
    Publication number: 20130283084
    Abstract: A method and system for error logging that is independent of the clock frequency ratio in an I/O subsystem. In one embodiment of the invention, the I/O subsystem has an error logging mechanism with a fixed queue depth of two and is independent of the clock frequencies in the I/O subsystem. The I/O subsystem has two queue entries for storing or logging the uncorrectable errors. In one embodiment of the invention, the I/O subsystem has two queue entries for storing or logging the 128-bit TLP Header and the First Error Pointer (FEP) of the uncorrectable errors detected in the I/O subsystem.
    Type: Application
    Filed: December 22, 2011
    Publication date: October 24, 2013
    Inventors: Ming Yi Lim, Su Wei Lim, Poh Thiam Teoh