Abstract: Methods and systems for improving fusion bonding are disclosed. Plasma treatment is performed on a substrate prior to the fusion bonding, which leaves residual charge on the substrate to be fusion bonded. The residual charge is usually dissipated through an electrically conductive silicone cushion on a loading pin. In the methods, the amount of residual voltage on a test silicon wafer is measured. If the residual voltage is too high, this indicates the usable lifetime of the silicone cushion has passed, and the electrically conductive silicone cushion is replaced. This ensures the continued dissipation of residual charge during use in production, improving the quality of fusion bonds between substrates.

Abstract: The present disclosure relates to exclusion rings for use in processing a semiconductor substrate in a processing chamber, such as a chemical vapor deposition chamber. The exclusion ring includes an alignment structure that cooperates with an alignment structure on a platen on which the exclusion ring will rest during processing of the wafer. The first alignment structure includes a guiding surface which promotes the reception of and positioning of the second alignment structure within the first alignment structure. Methods of utilizing the described exclusion rings are also described.

Abstract: Methods and systems for improving fusion bonding are disclosed. Plasma treatment is performed on a substrate prior to the fusion bonding, which leaves residual charge on the substrate to be fusion bonded. The residual charge is usually dissipated through an electrically conductive silicone cushion on a loading pin. In the methods, the amount of residual voltage on a test silicon wafer is measured. If the residual voltage is too high, this indicates the usable lifetime of the silicone cushion has passed, and the electrically conductive silicone cushion is replaced. This ensures the continued dissipation of residual charge during use in production, improving the quality of fusion bonds between substrates.

Abstract: Techniques to form low-resistance vias are discussed. In an example, semiconductor devices of a given row each include a semiconductor region extending in a first direction between corresponding source or drain regions, and a gate structure extending in a second direction over the semiconductor regions. Any semiconductor device may be separated from an adjacent semiconductor device along the second direction by a dielectric structure, through which a via passes. The via may include a conductive portion that extends through a dielectric wall in a third direction along at least an entire thickness of the gate structure. The conductive portion includes a conductive liner directly on the dielectric wall and a conductive fill on the conductive liner. The conductive liner comprises a pure elemental metal, such as tungsten, molybdenum, ruthenium, or a nickel aluminum alloy, with no metal nitride or barrier layer present between the conductive liner and the dielectric wall.

Abstract: The present disclosure relates to exclusion rings for use in processing a semiconductor substrate in a processing chamber, such as a chemical vapor deposition chamber. The exclusion ring includes an alignment structure that cooperates with an alignment structure on a platen on which the exclusion ring will rest during processing of the wafer. The first alignment structure includes a guiding surface which promotes the reception of and positioning of the second alignment structure within the first alignment structure. Methods of utilizing the described exclusion rings are also described.

Abstract: The present disclosure is directed to workpiece support for supporting a workpiece during semiconductor processing. The workpiece support includes one or more support frame bodies including a plurality of spaced apart spacers on a first surface of the support frame bodies. The spacers include a first surface spaced apart from the first surface of the support frame body. The spacing between the first surface of the spacers and the first surface of the support frame body results in the underside of the workpiece contacting the spacers but not contacting the first surface of the support frame body. Portions of the underside of the workpiece that do not contact the first surface of the support frame body are less susceptible to damage or accumulation of unwanted debris.

Abstract: Integrated circuit structures including an interconnect feature without a higher-resistance liner material. In absence of a liner, metal of low resistance directly contacts an adjacent dielectric material, enabling lower resistance interconnect. Even for low-k dielectric compositions, adhesion of the metal to the dielectric material is improved through the incorporation of nitrogen proximal to the interface. Prior to deposition of the metal upon a surface of the dielectric, the surface is exposed to nitrogen species to form a nitrogen-rich compound at the surface. The metal deposited upon the surface may then be nitrogen-lean, for example a substantially pure elemental metal or metal alloy.

Abstract: Methods and systems for improving fusion bonding are disclosed. Plasma treatment is performed on a substrate prior to the fusion bonding, which leaves residual charge on the substrate to be fusion bonded. The residual charge is usually dissipated through an electrically conductive silicone cushion on a loading pin. In the methods, the amount of residual voltage on a test silicon wafer is measured. If the residual voltage is too high, this indicates the usable lifetime of the silicone cushion has passed, and the electrically conductive silicone cushion is replaced. This ensures the continued dissipation of residual charge during use in production, improving the quality of fusion bonds between substrates.

Abstract: The present disclosure relates to exclusion rings for use in processing a semiconductor substrate in a processing chamber, such as a chemical vapor deposition chamber. The exclusion ring includes an alignment structure that cooperates with an alignment structure on a platen on which the exclusion ring will rest during processing of the wafer. The first alignment structure includes a guiding surface which promotes the reception of and positioning of the second alignment structure within the first alignment structure. Methods of utilizing the described exclusion rings are also described.

Abstract: A wireless transceiver module has a plurality of through holes and includes a wireless network chip, a circuit substrate, a Bluetooth chip, and a plurality of conductive connection structures. The Bluetooth chip is disposed between the circuit substrate and the wireless network chip, and the through holes are formed by passing through the wireless network chip, the circuit substrate, and the Bluetooth chip. The conductive connection structures are respectively disposed in the through hole. With the conductive connection structures, the Bluetooth chip, the wireless network chip, and the circuit substrate are electrically connected with each another.

Abstract: A wireless transceiver module has a plurality of through holes and includes a wireless network chip, a circuit substrate, a Bluetooth chip, and a plurality of conductive connection structures. The Bluetooth chip is disposed between the circuit substrate and the wireless network chip, and the through holes are formed by passing through the wireless network chip, the circuit substrate, and the Bluetooth chip. The conductive connection structures are respectively disposed in the through hole. With the conductive connection structures, the Bluetooth chip, the wireless network chip, and the circuit substrate are electrically connected with each another.