Patents by Inventor Ming-Yi Yang
Ming-Yi Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240130050Abstract: An embedded circuit board, made without gas bubbles or significant internal gaps according to a manufacturing method which is provided, includes an inner layer assembly, an embedded element, and first and second insulating elements. The inner layer assembly comprises a first main portion with opposing first and second surfaces and a first groove not extending to the second surface is positioned at the first surface. A first opening penetrates the second surface, and the first opening and the first groove are connected. The first groove carries electronic elements for embedment. The first insulating element covers the first surface and a surface of the embedded element away from the second surface. The second insulating element covers the second surface and extends into the first opening to be in contact with the embedded element.Type: ApplicationFiled: December 28, 2023Publication date: April 18, 2024Inventors: Cheng-Yi Yang, Hao-Wen Zhong, Biao Li, Ming-Jaan Ho, Ning Hou
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Publication number: 20240115681Abstract: Provided is a pharmaceutical composition including an active pharmaceutical ingredient, a toll-like receptor (TLR) agonist, a stimulator of interferon genes (STING) agonist, and a pharmaceutically acceptable carrier. Also provided are a method for inducing immune response and a method for treating or preventing cancer or an infectious disease, including administering an effective amount of the pharmaceutical composition to a subject in need thereof.Type: ApplicationFiled: September 28, 2023Publication date: April 11, 2024Applicant: National Health Research InstitutesInventors: Tsung-Hsien Chuang, Jing-Xing Yang, Jen-Chih Tseng, Zaida Nur Imana, Ming-Hsi Huang, Guann-Yi Yu
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Patent number: 11948837Abstract: A method for making a semiconductor structure includes: providing a substrate with a contact feature thereon; forming a dielectric layer on the substrate; etching the dielectric layer to form an interconnect opening exposing the contact feature; forming a metal layer on the dielectric layer and outside of the contact feature; and forming a graphene conductive structure on the metal layer, the graphene conductive structure filling the interconnect opening, being electrically connected to the contact feature, and having at least one graphene layer that extends in a direction substantially perpendicular to the substrate.Type: GrantFiled: August 30, 2021Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ching-Fu Yeh, Chin-Lung Chung, Shu-Wei Li, Yu-Chen Chan, Shin-Yi Yang, Ming-Han Lee
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Publication number: 20240088042Abstract: A semiconductor structure includes a dielectric layer over a substrate, a via conductor over the substrate and in the dielectric layer, and a first graphene layer disposed over the via conductor. In some embodiments, a top surface of the via conductor and a top surface of the dielectric layer are level. In some embodiments, the first graphene layer overlaps the via conductor from a top view. In some embodiments, the semiconductor structure further includes a second graphene layer under the via conductor and a third graphene layer between the dielectric layer and the via conductor. In some embodiments, the second graphene layer is between the substrate and the via conductor.Type: ApplicationFiled: January 11, 2023Publication date: March 14, 2024Inventors: SHU-WEI LI, HAN-TANG HUNG, YU-CHEN CHAN, CHIEN-HSIN HO, SHIN-YI YANG, MING-HAN LEE, SHAU-LIN SHUE
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Publication number: 20240087990Abstract: Embodiments of the present disclosure provide a method for forming a semiconductor package. In one embodiment, the method includes providing a first integrated circuit die having a first circuit design on a substrate, providing a second integrated circuit die having a second circuit design on the substrate, wherein the first and second integrated circuit dies are separated from each other by a scribe line.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Inventors: Shin-Yi YANG, Ming-Han LEE, Shau-Lin SHUE
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Patent number: 11929326Abstract: Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a third dielectric layer over the second dielectric layer, a second contact feature extending through the second dielectric layer and the third dielectric layer, and a graphene layer between the second contact feature and the third dielectric layer.Type: GrantFiled: December 20, 2021Date of Patent: March 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shin-Yi Yang, Ming-Han Lee, Shau-Lin Shue
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Publication number: 20240081081Abstract: A ferroelectric memory device and a semiconductor die are provided. The ferroelectric memory device includes a gate electrode; a channel layer, overlapped with the gate electrode; source/drain contacts, in contact with separate ends of the channel layer; a ferroelectric layer, lying between the gate electrode and the channel layer; and a first insertion layer, extending in between the ferroelectric layer and the channel layer, and comprising a metal carbonitride or a metal nitride.Type: ApplicationFiled: January 10, 2023Publication date: March 7, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ya-Ling Lee, Chung-Te Lin, Han-Ting Tsai, Wei-Gang Chiu, Yen-Chieh Huang, Ming-Yi Yang
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Publication number: 20240071822Abstract: A method for manufacturing a semiconductor structure includes forming a first interconnect feature in a first dielectric feature, the first interconnect feature including a first conductive element exposed from the first dielectric feature; forming a first cap feature over the first conductive element, the first cap feature including a first cap element which includes a two-dimensional material; forming a second dielectric feature with a first opening that exposes the first cap element; forming a barrier layer over the second dielectric feature while exposing the first cap element from the barrier layer; removing a portion of the first cap element exposed from the barrier layer; and forming a second conductive element in the first opening.Type: ApplicationFiled: August 31, 2022Publication date: February 29, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Lung CHUNG, Shin-Yi YANG, Yu-Chen CHAN, Han-Tang HUNG, Shu-Wei LI, Ming-Han LEE
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Patent number: 7989920Abstract: A phase change memory is provided. The method includes forming contact plugs in a first dielectric layer. A second dielectric layer is formed overlying the first dielectric layer and a trench formed therein exposing portions of the contact plugs. A metal layer is formed over surfaces of the trench. One or more heaters are formed from the metal layer such that each heater is formed along one or more sidewalls of the trench, wherein the portion of the heater along the sidewalls does not include a corner region of adjacent sidewalls. The trench is filled with a third dielectric layer, and a fourth dielectric layer is formed over the third dielectric layer. Trenches are formed in the fourth dielectric layer and filled with a phase change material. An electrode is formed over the phase change material.Type: GrantFiled: February 10, 2010Date of Patent: August 2, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzyh-Cheang Lee, Ming-Yi Yang, Fu-Liang Yang, Denny Duan-Iee Tang
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Publication number: 20110025442Abstract: A common mode filter comprises an insulating substrate, a lower coil leading layer, a coil main body multilayer, and an upper coil leading layer. The upper coil leading layer comprises at least one upper lead, at least one upper terminal, and at least one upper contact, and the lower coil leading layer comprises at least one lower lead, at least one lower terminal, and at least one lower contact. The two ends of the upper lead are respectively connected to the upper terminal and the upper contact, and the upper lead surrounds the upper contact. The two ends of the lower lead are respectively connected to the lower terminal and the lower contact, and the lower lead surrounds the lower contact. The upper coil leading layer and the lower coil leading layer sandwich the coil main body multi-layer, and the lower coil leading layer is disposed on the insulating substrate.Type: ApplicationFiled: March 18, 2010Publication date: February 3, 2011Applicant: INPAQ TECHNOLOGY CO., LTD.Inventors: MING LIANG HSIEH, MING YI YANG, LIANG CHIEH WU, SHENG FU SU, CHENG YI WANG
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Patent number: 7821368Abstract: A thin film type common mode noise filter and its fabrication method are disclosed. There are several electric insulation layers, coil lead layers and main coil layers are formed on an insulation substrate by means of processes of Lithography, Physical Vapor Deposition, etching or other chemical process. After that the structure is covered with an electric insulation gluing layer and a magnetic material layer so as to form a thin film type common mode noise filter with a low production cost but an improved filtering characteristic of the common mode noise.Type: GrantFiled: May 27, 2009Date of Patent: October 26, 2010Assignee: Inpaq Technology Co., Ltd.Inventors: Ming Yi Yang, Zheng Yi Wang, Ming Liang Hsieh, Sheng Fu Su
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Publication number: 20100140580Abstract: A phase change memory is provided. The method includes forming contact plugs in a first dielectric layer. A second dielectric layer is formed overlying the first dielectric layer and a trench formed therein exposing portions of the contact plugs. A metal layer is formed over surfaces of the trench. One or more heaters are formed from the metal layer such that each heater is formed along one or more sidewalls of the trench, wherein the portion of the heater along the sidewalls does not include a corner region of adjacent sidewalls. The trench is filled with a third dielectric layer, and a fourth dielectric layer is formed over the third dielectric layer. Trenches are formed in the fourth dielectric layer and filled with a phase change material. An electrode is formed over the phase change material.Type: ApplicationFiled: February 10, 2010Publication date: June 10, 2010Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzyh-Cheang Lee, Ming-Yi Yang, Fu-Liang Yang, Denny Duan-lee Tang
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Patent number: 7705424Abstract: A phase change memory is provided. The method includes forming contact plugs in a first dielectric layer. A second dielectric layer is formed overlying the first dielectric layer and a trench formed therein exposing portions of the contact plugs. A metal layer is formed over surfaces of the trench. One or more heaters are formed from the metal layer such that each heater is formed along one or more sidewalls and a portion of the bottom of the trench, wherein the portion of the heater along the sidewalls does not include a corner region of adjacent sidewalls. The trench is filled with a third dielectric layer, and a fourth dielectric layer is formed over the third dielectric layer. Trenches are formed in the fourth dielectric layer and filled with a phase change material. An electrode is formed over the phase change material.Type: GrantFiled: May 15, 2007Date of Patent: April 27, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzyh-Cheang Lee, Ming-Yi Yang, Fu-Liang Yang, Denny Duan-Iee Tang
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Publication number: 20080285328Abstract: A phase change memory is provided. The method includes forming contact plugs in a first dielectric layer. A second dielectric layer is formed overlying the first dielectric layer and a trench formed therein exposing portions of the contact plugs. A metal layer is formed over surfaces of the trench. One or more heaters are formed from the metal layer such that each heater is formed along one or more sidewalls and a portion of the bottom of the trench, wherein the portion of the heater along the sidewalls does not include a corner region of adjacent sidewalls. The trench is filled with a third dielectric layer, and a fourth dielectric layer is formed over the third dielectric layer. Trenches are formed in the fourth dielectric layer and filled with a phase change material. An electrode is formed over the phase change material.Type: ApplicationFiled: May 15, 2007Publication date: November 20, 2008Inventors: Tzyh-Cheang Lee, Ming-Yi Yang, Fu-Liang Yang, Denny Duan-lee Tang