Patents by Inventor Ming-Yih Kao

Ming-Yih Kao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11923378
    Abstract: The present disclosure provides an electronic device including a substrate, a common electrode, and a plurality of pixels. The common electrode is disposed on the substrate. The pixels are disposed on the substrate, and at least one of the pixels includes a thin film transistor, a first electrode, a second electrode, and an auxiliary electrode. The first electrode is electrically connected to the thin film transistor. The auxiliary electrode is partially overlapped with the first electrode in a top view direction of the electronic device. The auxiliary electrode is electrically connected to the common electrode and electrically isolated from the first electrode, and the first electrode and the auxiliary electrode have a minimum distance less than a minimum distance between the first electrode and the common electrode.
    Type: Grant
    Filed: February 20, 2023
    Date of Patent: March 5, 2024
    Assignee: InnoLux Corporation
    Inventors: Chi-Lun Kao, Ker-Yih Kao, Ming-Chun Tseng, Kung-Chen Kuo
  • Patent number: 9202905
    Abstract: Embodiments include apparatuses and methods related to an HFET. In embodiments, one or all of the buffer layer, the back-barrier layer, or the barrier layer may be formed of a digital alloy. In embodiments, the digital alloy may include alternating layers of alloys of aluminum, gallium, and nitrogen. Other embodiments may be disclosed or claimed herein.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: December 1, 2015
    Assignee: TriQuint Semiconductor, Inc.
    Inventors: Jinqiao Xie, Edward A. Beam, III, Ming-Yih Kao, Hua-Quen Tserng, Paul Saunier
  • Patent number: 7541232
    Abstract: A method for fabricating devices in a multi-layer structure adapted for the formation of enhancement mode high electron mobility transistors, depletion mode high electron mobility transistors, and power high electron mobility transistors includes defining gate recesses in the structure. The structure has, on a substrate, a channel layer, spacer layer on the channel layer, a first Schottky layer, a second Schottky layer on the first Schottky layer, and a third Schottky layer on the second Schottky layer, and a contact layer on the third Schottky layer. Etch stops are defined intermediate the first and second Schottky layers, intermediate the second and third Schottky layers, and intermediate the third Schottky layer and the contact layer.
    Type: Grant
    Filed: November 28, 2007
    Date of Patent: June 2, 2009
    Assignee: Lockheed Martin Corporation
    Inventors: Kevin L. Robinson, Larry Witkowski, Ming-Yih Kao
  • Publication number: 20080090345
    Abstract: A method for fabricating devices in a multi-layer structure adapted for the formation of enhancement mode high electron mobility transistors, depletion mode high electron mobility transistors, and power high electron mobility transistors includes defining gate recesses in the structure. The structure has, on a substrate, a channel layer, spacer layer on the channel layer, a first Schottky layer, a second Schottky layer on the first Schottky layer, and a third Schottky layer on the second Schottky layer, and a contact layer on the third Schottky layer. Etch stops are defined intermediate the first and second Schottky layers, intermediate the second and third Schottky layers, and intermediate the third Schottky layer and the contact layer.
    Type: Application
    Filed: November 28, 2007
    Publication date: April 17, 2008
    Inventors: Kevin Robinson, Larry Witkowski, Ming-Yih Kao
  • Patent number: 7321132
    Abstract: A multi-layer structure for use in the fabrication of integrated circuit devices is adapted for the formation of enhancement mode high electron mobility transistors, depletion mode high electron mobility transistors, and power high electron mobility transistors. The structure has, on a substrate, a channel layer, spacer layer on the channel layer, a first Schottky layer, a second Schottky layer on the first Schottky layer, and a third Schottky layer on the second Schottky layer, and a contact layer on the third Schottky layer. Etch stops are defined intermediate the first and second Schottky layers, intermediate the second and third Schottky layers, and intermediate the third Schottky layer and the contact layer.
    Type: Grant
    Filed: March 15, 2005
    Date of Patent: January 22, 2008
    Assignee: Lockheed Martin Corporation
    Inventors: Kevin L. Robinson, Larry Witkowski, Ming-Yih Kao
  • Publication number: 20060208279
    Abstract: A multi-layer structure for use in the fabrication of integrated circuit devices is adapted for the formation of enhancement mode high electron mobility transistors, depletion mode high electron mobility transistors, and power high electron mobility transistors. The structure has, on a substrate, a channel layer, spacer layer on the channel layer, a first Schottky layer, a second Schottky layer on the first Schottky layer, and a third Schottky layer on the second Schottky layer, and a contact layer on the third Schottky layer. Etch stops are defined intermediate the first and second Schottky layers, intermediate the second and third Schottky layers, and intermediate the third Schottky layer and the contact layer.
    Type: Application
    Filed: March 15, 2005
    Publication date: September 21, 2006
    Inventors: Kevin Robinson, Larry Witkowski, Ming-Yih Kao
  • Publication number: 20040178422
    Abstract: A high electron mobility transistor is constructed with a substrate, a lattice-matching buffer layer formed on the substrate, and a heavily doped p-type barrier layer formed on the buffer layer. A spacer layer is formed on the barrier layer, and a channel layer is formed on the spacer layer. The channel layer may be of uniform composition, or may be made from two or more sublayers. A Schottky layer is formed over the channel layer, and source and drain contacts are formed on the Schottky layer. The substrate may be gallium arsenide, indium phosphide, or other suitable material, and the various semiconductor layers formed over the substrate contain indium. The transistor's transition frequency of the transistor is above 200 GHz.
    Type: Application
    Filed: March 14, 2003
    Publication date: September 16, 2004
    Applicant: TriQuint Semiconductor, Inc.
    Inventors: Hua Quen Tserng, Edward A. Beam, Ming-Yih Kao
  • Patent number: 6787826
    Abstract: A high electron mobility transistor is constructed with a substrate, a lattice-matching buffer layer formed on the substrate, and a heavily doped p-type barrier layer formed on the buffer layer. A spacer layer is formed on the barrier layer, and a channel layer is formed on the spacer layer. The channel layer may be of uniform composition, or may be made from two or more sublayers. A Schottky layer is formed over the channel layer, and source and drain contacts are formed on the Schottky layer. The substrate may be gallium arsenide, indium phosphide, or other suitable material, and the various semiconductor layers formed over the substrate contain indium. The transistor's transition frequency of the transistor is above 200 GHz.
    Type: Grant
    Filed: March 14, 2003
    Date of Patent: September 7, 2004
    Assignee: TriQuint Semiconductor, Inc.
    Inventors: Hua Quen Tserng, Edward A. Beam, III, Ming-Yih Kao
  • Patent number: 6697412
    Abstract: A light-emitting device includes a GaAs substrate, a light-emitting structure disposed above the substrate and capable of emitting light having a wavelength of about 1.3 microns to about 1.55 microns, and a buffer layer disposed between the substrate and the light-emitting structure. The composition of the buffer layer varies through the buffer layer such that a lattice constant of the buffer layer grades from a lattice constant approximately equal to a lattice constant of the substrate to a lattice constant approximately equal to a lattice constant of the light-emitting structure. The light-emitting device exhibits improved mechanical, electrical, thermal, and optical properties compared to similar light-emitting devices grown on InP substrates.
    Type: Grant
    Filed: April 13, 2001
    Date of Patent: February 24, 2004
    Assignee: TriQuint Semiconductor, Inc.
    Inventors: Edward A. Beam, III, Gary A. Evans, Paul Saunier, Ming-Yih Kao, David M. Fanning, William H. Davenport, Andy Turudic, Walter A. Wohlmuth
  • Publication number: 20020150137
    Abstract: A light-emitting device includes a GaAs substrate, a light-emitting structure disposed above the substrate and capable of emitting light having a wavelength of about 1.3 microns to about 1.55 microns, and a buffer layer disposed between the substrate and the light-emitting structure. The composition of the buffer layer varies through the buffer layer such that a lattice constant of the buffer layer grades from a lattice constant approximately equal to a lattice constant of the substrate to a lattice constant approximately equal to a lattice constant of the light-emitting structure. The light-emitting device exhibits improved mechanical, electrical, thermal, and optical properties compared to similar light-emitting devices grown on InP substrates.
    Type: Application
    Filed: April 13, 2001
    Publication date: October 17, 2002
    Inventors: Edward A. Beam, Gary A. Evans, Paul Saunier, Ming-Yih Kao, David M. Fanning, William H. Davenport, Andy Turudic, Walter A. Wohlmuth
  • Patent number: 6100477
    Abstract: A novel micro-electro-mechanical (MEMS) RF switch having a cavity (32) in a substrate (28) which creates a spacing between a conductive membrane (34) and a bottom electrode (38). The invention eliminates the need for the dielectric posts found in prior art MEMS RF switches, includes a flexure structure (36) in the membrane (34) which will reduce the required pull down voltage for the membrane, and reduces the stress and fatigue in the membrane due to switch activation.
    Type: Grant
    Filed: July 17, 1998
    Date of Patent: August 8, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: John Neal Randall, Ming-Yih Kao