Patents by Inventor Ming-Yih Wang
Ming-Yih Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145461Abstract: A modulation device includes a substrate, an electrostatic discharge protection element, an electronic element, and a driving element. The substrate has an active region. The electrostatic discharge protection element is arranged around the active region. The electronic element is disposed in the active region. The driving element is electrically connected to the electronic element.Type: ApplicationFiled: October 4, 2023Publication date: May 2, 2024Applicant: Innolux CorporationInventors: Ker-Yih Kao, Tong-Jung Wang, Wen-Chieh Lin, Ming-Chun Tseng, Yi-Hung Lin
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Patent number: 11963347Abstract: A memory device includes a transistor, an anti-fuse element, a source/drain contact, a first gate via, and a second gate via. The transistor is over a substrate. The anti-fuse element is over the substrate and is connected to the transistor in series. The source/drain contact is connected to a source/drain region of the transistor. The first gate via is connected to a first gate structure of the transistor. The first gate structure of the transistor extends along a first direction in a top view. The second gate via is connected to a second gate structure of the anti-fuse element. The second gate via is between the first gate via and the source/drain contact along the first direction in the top view.Type: GrantFiled: April 21, 2023Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chiung-Ting Ou, Ming-Yih Wang, Jian-Hong Lin
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Publication number: 20240075449Abstract: The application relates to a polymerization vessel and a method for manufacturing the same. An interior surface of the polymerization vessel has a specific structure, so that the polymerization vessel has better heat transfer efficiency. Closed cooling channels are constructed from the specific structure, and therefore cooling fluid flows in the closed cooling channels. Furthermore, there won't be any by-pass defects in the cooling channels of the polymerization vessel, thereby improving cooling efficiency of the cooling fluid.Type: ApplicationFiled: March 30, 2023Publication date: March 7, 2024Inventors: Ming-Hung CHENG, Fuh-Yih SHIH, Shih-Ming YEH, Wen-Yi WANG
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Publication number: 20240047345Abstract: A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a package structure. The package structure includes a passivation layer formed over an interconnect structure; an electrically-conductive structure formed on the passivation layer and extending through the passivation layer to electrically contact the interconnect structure; a dielectric structure formed over the passivation layer and surrounding the electrically-conductive structure to expose at least a portion of a top surface of the electrically-conductive structure; and a metallic protection structure formed on the top surface of the electrically-conductive structure exposed from the dielectric structure. The top surface of the metallic protection structure is aligned with or lower than a top surface of the dielectric structure.Type: ApplicationFiled: October 19, 2023Publication date: February 8, 2024Inventors: CHUN-WEI CHANG, HSUAN-MING HUANG, JIAN-HONG LIN, MING-HONG HSIEH, MINGNI CHANG, MING-YIH WANG
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Patent number: 11852682Abstract: A circuit screening system including a target circuit under test receiving a first testing signal in a first period and a second testing signal in a second period; a power circuit providing a supply voltage to the target circuit under test, the supply voltage maintaining at a first voltage level in the first period and deviating from the first voltage level, and maintaining at the first voltage level in the second period; and a clock generating circuit providing a clock signal to the target circuit under test, the clock signal triggering the target circuit under test to receive the first testing signal in the first period and the second testing signal in the second period; the clock signal having a first profile and a second profile in the first period and the second period, respectively, and the first profile and the second profile having a phase difference.Type: GrantFiled: November 14, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chi-Che Wu, Tsung-Yang Hung, Jia-Ming Guo, Yi-Na Fang, Ming-Yih Wang
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Publication number: 20230386973Abstract: An integrated circuit (IC) with through-circuit vias (TCVs) and methods of forming the same are disclosed. The IC includes a semiconductor device, first and second interconnect structures disposed on first and second surfaces of the semiconductor device, respectively, first and second inter-layer dielectric (ILD) layers disposed on front and back surfaces of the substrate, respectively, and a TCV disposed within the first and second interconnect structures, the first and second ILD layers, and the substrate. The TCV is spaced apart from the semiconductor device by a portion of the substrate and portions of the first and second ILD layers. A first end of the TCV, disposed over the front surface of the substrate, is connected to a conductive line of the first interconnect structure and a second end of the TCV, disposed over the back surface of the substrate, is connected to a conductive line of the second interconnect structure.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jian-Hong LIN, Hsin-Chun CHANG, Ming-Hong HSIEH, Ming-Yih WANG, Yinlung LU
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Patent number: 11830806Abstract: A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a package structure. The package structure includes a passivation layer formed over an interconnect structure; an electrically-conductive structure formed on the passivation layer and extending through the passivation layer to electrically contact the interconnect structure; a dielectric structure formed over the passivation layer and surrounding the electrically-conductive structure to expose at least a portion of a top surface of the electrically-conductive structure; and a metallic protection structure formed on the top surface of the electrically-conductive structure exposed from the dielectric structure. The top surface of the metallic protection structure is aligned with or lower than a top surface of the dielectric structure.Type: GrantFiled: April 29, 2021Date of Patent: November 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chun-Wei Chang, Hsuan-Ming Huang, Jian-Hong Lin, Ming-Hong Hsieh, Mingni Chang, Ming-Yih Wang
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Patent number: 11830832Abstract: A semiconductor structure is provided. The semiconductor structure includes a metallization structure with a dielectric surface. A first protecting structure over the dielectric surface. A first protecting structure over the passivation layer. A conductive pad over the dielectric surface. A polymer layer over the first protecting structure and the conductive pad. A conductive bump electrically coupled to the conductive pad through an opening of the polymer layer. A first portion of the first protecting structure is leveled with the conductive pad and a second portion of the first protecting structure is higher than the conductive pad.Type: GrantFiled: March 19, 2021Date of Patent: November 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tung-Jiun Wu, Mingni Chang, Ming-Yih Wang, Yinlung Lu
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Publication number: 20230284442Abstract: A memory device includes a transistor, an anti-fuse element, a source/drain contact, a first gate via, and a second gate via. The transistor is over a substrate. The anti-fuse element is over the substrate and is connected to the transistor in series. The source/drain contact is connected to a source/drain region of the transistor. The first gate via is connected to a first gate structure of the transistor. The first gate structure of the transistor extends along a first direction in a top view. The second gate via is connected to a second gate structure of the anti-fuse element. The second gate via is between the first gate via and the source/drain contact along the first direction in the top view.Type: ApplicationFiled: April 21, 2023Publication date: September 7, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chiung-Ting OU, Ming-Yih WANG, Jian-Hong LIN
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Publication number: 20230273257Abstract: An apparatus for testing a device under test (DUT) is provided. The apparatus includes a power supply device and a data generating device. The power supply device is configured to provide a first voltage and a second voltage to the DUT. The data generating device is configured to provide first data to the DUT. The power supply device is configured to provide the first voltage to the DUT in a first time duration. The data generating device is configured to provide the first data to the DUT in the first time duration. The power supply device is configured to provide the second voltage to the DUT in a second time duration after the first time duration. The second voltage is different from the first voltage.Type: ApplicationFiled: April 28, 2023Publication date: August 31, 2023Inventors: CHI-CHE WU, TSUNG-YANG HUNG, MING-YIH WANG, JIA-MING GUO
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Publication number: 20230194598Abstract: A method is provided and includes several operations: testing multiple scan chains in multiple shift cycles to obtain multiple values; determining at least one fail chain in the scan chains and determining at least one fail shift cycle corresponding to at least one fail value in the values; mapping the at least one fail chain and the at least one fail shift cycle to the scan chains to identify the at least one fail flip flop; and identifying at least one fault site corresponding to the at least one fail flip flop.Type: ApplicationFiled: February 9, 2023Publication date: June 22, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chi-Che WU, Tsung-Yang HUNG, Ming-Yih WANG
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Patent number: 11675004Abstract: An apparatus for testing a device under test (DUT) is provided. The apparatus includes a power supply device and a data generating device. The power supply device is configured to provide a first voltage and a second voltage to the DUT. The data generating device is configured to provide first data to the DUT. The power supply device is configured to provide the first voltage to the DUT in a first time duration. The data generating device is configured to provide the first data to the DUT in the first time duration. The power supply device is configured to provide the second voltage to the DUT in a second time duration after the first time duration. The second voltage is different from the first voltage.Type: GrantFiled: August 10, 2020Date of Patent: June 13, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chi-Che Wu, Tsung-Yang Hung, Ming-Yih Wang, Jia-Ming Guo
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Patent number: 11665890Abstract: A memory device includes a transistor, an anti-fuse element, a first gate via, a second gate via, and a bit line. The transistor includes a fin structure and a first gate structure across the fin structure. The anti-fuse element includes the fin structure and a second gate structure across the fin structure. The first gate via is connected to the first gate structure of the transistor and is spaced apart from the fin structure in a top view. The second gate via is connected to the second gate structure of the anti-fuse element and is directly above the fin structure. The bit line is connected to the fin structure and the transistor.Type: GrantFiled: August 4, 2021Date of Patent: May 30, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chiung-Ting Ou, Ming-Yih Wang, Jian-Hong Lin
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Patent number: 11616002Abstract: An integrated circuit (IC) with through-circuit vias (TCVs) and methods of forming the same are disclosed. The IC includes a semiconductor device, first and second interconnect structures disposed on first and second surfaces of the semiconductor device, respectively, first and second inter-layer dielectric (ILD) layers disposed on front and back surfaces of the substrate, respectively, and a TCV disposed within the first and second interconnect structures, the first and second ILD layers, and the substrate. The TCV is spaced apart from the semiconductor device by a portion of the substrate and portions of the first and second ILD layers. A first end of the TCV, disposed over the front surface of the substrate, is connected to a conductive line of the first interconnect structure and a second end of the TCV, disposed over the back surface of the substrate, is connected to a conductive line of the second interconnect structure.Type: GrantFiled: January 29, 2021Date of Patent: March 28, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jian-Hong Lin, Hsin-Chun Chang, Ming-Hong Hsieh, Ming-Yih Wang, Yinlung Lu
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Publication number: 20230070575Abstract: A circuit screening system including a target circuit under test receiving a first testing signal in a first period and a second testing signal in a second period; a power circuit providing a supply voltage to the target circuit under test, the supply voltage maintaining at a first voltage level in the first period and deviating from the first voltage level, and maintaining at the first voltage level in the second period; and a clock generating circuit providing a clock signal to the target circuit under test, the clock signal triggering the target circuit under test to receive the first testing signal in the first period and the second testing signal in the second period; the clock signal having a first profile and a second profile in the first period and the second period, respectively, and the first profile and the second profile having a phase difference.Type: ApplicationFiled: November 14, 2022Publication date: March 9, 2023Inventors: CHI-CHE WU, TSUNG-YANG HUNG, JIA-MING GUO, YI-NA FANG, MING-YIH WANG
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Patent number: 11579191Abstract: A method is provided in the present disclosure. The method includes several operations: generating, by a processing unit, a mapping table associated with multiple scan chains and multiple shift cycles corresponding to multiple values stored in the scan chains in an integrated circuit; determining, based on the mapping table, at least one fail flip flop in the scan chains in response to the values outputted from the scan chains; and identifying at least one fault site corresponding to the at least one fail flip flop.Type: GrantFiled: September 16, 2020Date of Patent: February 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chi-Che Wu, Tsung-Yang Hung, Ming-Yih Wang
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Publication number: 20230019641Abstract: A method includes acquiring a design layout of a standard cell, extracting feature information of one or more vias in the standard cell from the design layout, performing a circuit simulation to obtain first simulation outputs of the standard cell for input patterns by applying a first abnormal resistance value as a parasitic resistance value of a first via among the one or more vias, the first abnormal resistance value being different from a nominal parasitic resistance value of the first via, determining whether the first simulation outputs match corresponding expected outputs of the standard cell for the input patterns, and in response to one or more simulation outputs among the first simulation outputs not matching the corresponding expected outputs, recording one or more defect types for the first via having the first abnormal resistance value along with corresponding input patterns and corresponding simulation outputs.Type: ApplicationFiled: January 10, 2022Publication date: January 19, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Yi LIN, Tsung-Yang Hung, Ankita Patidar, Ming-Yih Wang, Sandeep Kumar Goel
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Publication number: 20230005847Abstract: A method includes forming a plurality of low-k dielectric layers over a semiconductor substrate, forming a first plurality of dummy stacked structures extending into at least one of the plurality of low-k dielectric layers, forming a plurality of non-low-k dielectric layers over the plurality of low-k dielectric layers, and forming a second plurality of dummy stacked structures extending into the plurality of non-low-k dielectric layers. The second plurality of dummy stacked structures are over and connected to corresponding ones of the first plurality of dummy stacked structures. The method further includes etching the plurality of non-low-k dielectric layers, the plurality of low-k dielectric layers, and the semiconductor substrate to form a via opening. The via opening is encircled by the first plurality of dummy stacked structures and the second plurality of dummy stacked structures. The via opening is then filled to form a through-via.Type: ApplicationFiled: September 2, 2021Publication date: January 5, 2023Inventors: Mingni Chang, Yun-Chin Tsou, Ching-Jing Wu, Shiou-Fan Chen, Ming-Yih Wang
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Publication number: 20220367323Abstract: An integrated circuit (IC) with through-circuit vias (TCVs) and methods of forming the same are disclosed. The IC includes a semiconductor device, first and second interconnect structures disposed on first and second surfaces of the semiconductor device, respectively, first and second inter-layer dielectric (ILD) layers disposed on front and back surfaces of the substrate, respectively, and a TCV disposed within the first and second interconnect structures, the first and second ILD layers, and the substrate. The TCV is spaced apart from the semiconductor device by a portion of the substrate and portions of the first and second ILD layers. A first end of the TCV, disposed over the front surface of the substrate, is connected to a conductive line of the first interconnect structure and a second end of the TCV, disposed over the back surface of the substrate, is connected to a conductive line of the second interconnect structure.Type: ApplicationFiled: July 29, 2022Publication date: November 17, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jian-Hong Lin, Hsin-Chun Chang, Ming-Hong Hsieh, Ming-Yih Wang, Yinlung Lu
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Patent number: 11500016Abstract: A circuit screening system includes a target circuit under test, a power circuit, and a clock generating circuit. The target circuit under test receives a first testing signal in a first period, and a second testing signal in a second period, and the first testing signal is different from the second testing signal. The power circuit provides a supply voltage to the target circuit under test, wherein a voltage level of the supply voltage maintains at a first voltage level in the first period, is pulled up to a second voltage level and back to the first level after the first period, and maintains at the first voltage level in a second period after the first period. The clock generating circuit provides a clock signal to the target circuit under test, wherein the clock signal has different profiles in the first period and the second period.Type: GrantFiled: December 7, 2020Date of Patent: November 15, 2022Assignee: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Chi-Che Wu, Tsung-Yang Hung, Jia-Ming Guo, Edna Fang, Ming-Yih Wang