Abstract: A fabrication method for an integrated device having a capacitor in an interconnect system is described. At least a first exposed metal line and a second metal line are provided in an insulating layer. A stack layer is deposited and patterned to form a film stack structure over the second metal line. An inter-metal dielectric layer is formed over the film stack structure, the first metal line and the insulating layer. At least a first dual damascene interconnect and a second dual damascene interconnect are formed over and in contact with the first metal line and the film stack structure, respectively.

Abstract: A fabrication method for an integrated device having a capacitor in an interconnect system is described. At least a first exposed metal line and a second metal line are provided in an insulating layer. A stack layer is deposited and patterned to form a film stack structure over the second metal line. An inter-metal dielectric layer is formed over the film stack structure, the first metal line and the insulating layer. At least a first dual damascene interconnect and a second dual damascene interconnect are formed over and in contact with the first metal line and the film stack structure, respectively.

Abstract: The present invention provides a method to form a titanium-containing glue layer and to reduce the diffusion of boron ion into a titanium-containing glue layer. The primary step is a nitrogen-ion implantation process in which the nitrogen ions are implanted into an interface region between a boron-ion doped region and a titanium-containing glue layer to form a nitrogen-ion-containing doped region. Afterward, a titanium-containing glue layer is conformally deposited on the surface of the nitrogen-ion-containing doped region by a TiCl4-based CVD method. Because the temperature used in the CVD is so high that an ion diffusion occurs in the interface region between the nitrogen-ion-containing doped region and the titanium-containing glue layer, a titanium nitride layer is then formed in the interface region by a contact of the titanium ions and the nitrogen ions. The boron ions can not pass through the nitrogen-ion-containing doped region and the titanium nitride layer into the titanium-containing glue layer.

Abstract: Submicron-dimensioned, MOSFET devices are formed using multiple implants for forming an impurity concentration distribution profile exhibiting three impurity concentration peaks at a predetermined depths below the semiconductor surface substrate. The inventive method reduces “latch-up” and “punch-through” with controllable adjustment of the threshold voltage.

Abstract: Silicon-based, submicron-dimensioned MOS and/or CMOS transistor devices having substantially reduced source/drain junction-to-semiconductor substrate capacitance are formed by implanting oxygen atoms and/or molecules just below source/drain implant regions. Implantation conditions are selected to provide a peak oxygen implant concentration at a depth just below the ultimate source/drain junction depth. Subsequent thermal processing at elevated temperature results in source/drain dopant diffusion/activation and formation of a silicon oxide barrier layer or stratum just below the ultimate source/drain junction depth, thereby substantially reducing junction-to-substrate capacitance of refractory metal silicide-contact devices.

Abstract: Submicron-dimensioned MOS and/or CMOS transistors are fabricated by a process employing removable sidewall spacers made of a material, such as UV-nitride, which is readily etched in its as-deposited, undensified state but difficult-to-etch in its thermally annealed, densified state. The as-deposited, undensified spacers are removed by etching with dilute aqueous HF after implantation of moderately or heavily-doped source/drain regions but prior to annealing of the implants for dopant diffusion/activation and lattice damage relaxation. Lightly- or moderately doped, shallow-depth source/drain extensions are implanted and annealed after spacer removal.

Abstract: A semiconductor device having a retrograde channel profile is achieved by forming a retrograde impurity region in the surface portion of a semiconductor substrate, and subsequently forming a semiconductor layer on the retrograde impurity region at a predetermined thickness. The thickness of the semiconductor layer is controlled to localize the retrograde impurity region and its impurity concentration peak at a predetermined depth, thereby reducing the device's susceptibility to “reverse short channel effects.

Abstract: Submicron-dimensioned, p-channel MOS transistors and CMOS devices a formed using nitrogen and boron co-implants for forming p-type well regions, each implant having a parabolically-shaped concentration distribution profile. During subsequent thermal annealling, boron-doped wells are formed, each having a retrograde-shaped concentration distribution profile exhibiting a peak boron concentration at a preselected depth below the semiconductor substrate surface. The inventive method reduces “short-channel” effects such as “punch-through” while maintaining high channel mobility.

Abstract: Short channel effects are curtailed thereby increasing integrated circuit speed by forming a channel dopant with an asymmetric impurity concentration profile. Embodiments include ion implanting Si or Ge at a large tilt angle to amorphize a portion of a designated channel region with a varying degree of amorphization decreasing from the intended drain region to the intended source region, substantially vertically ion implanting channel dopant impurities and annealing. During annealing, diffusion is retarded in areas of increased amorphization, thereby forming an asymmetric impurity concentration gradient across the channel region increasing in the direction of the source region.

Abstract: Submicron-dimensioned, silicon-based MOS-type transistor devices having reduced tendency for “latch up” are formed by removing residual indium dopant utilized for forming a retrograde-shaped indium doping concentration profile of the channel region from the surface and uppermost stratum of the silicon substrate by a rapid thermal annealing process prior to silicon oxide thin gate insulator formation. The inventive methodology substantially eliminates deleterious indium contamination of the gate insulator layer.

Abstract: A transistor having reduced series resistance and method for producing the same. The method reduces transistor series resistance by implanting nitrogen into an nLDD/Source/Drain extension region of the transistor. The nitrogen implantation in connection with the implantation of a conventional n-type dopant (e.g. arsenic or phosphorus), results in a transistor having low series resistance, reduced hot carrier effects and no significant increase in source/drain extension overlap.

Abstract: Sub-micron-dimensioned, asymmetrically-configured MOS and/or CMOS transistors are fabricated using removable sidewall spacers made of a material, such as UV-nitride, one of which is selectively treated subsequent to deposition, e.g., by ion implantation, to augment the etch rate thereof with a room temperature etchant, e.g., dilute aqueous HF. The treated spacer is removed with the dilute, aqueous HF prior to implantation of asymmetrically-configured, moderately or heavily-doped source/drain regions but prior to any post-implantation annealing processing, in order not to increase the etch resistance of the spacer material by thermally-induced densification.

Abstract: Submicron-dimensioned MOS and/or CMOS transistors are fabricated by a process employing removable sidewall spacers made of a material, such as UV-nitride, which is readily etched in its as-deposited, undensified state but difficult-to-etch in its thermally annealed, densified state. The as-deposited, undensified spacers are removed by etching with dilute aqueous HF after implantation of heavily-sloped source/drain junction regions but prior to annealing of the implant for dopant diffusion/activation and lattice damage relaxation. Lightly-or moderately doped, shallow-depth source/drain extensions are implanted and annealed after spacer removal.

Abstract: Submicron-dimensioned devices are formed whereby a desired relationship between the impurity concentration peak and a lightly doped source/drain region is obtained.

Abstract: A method of fabricating a MOS transistor having SEG Si. After the formation of a gate and a spacer and before a source/drain region is formed, a selective epitaxial growth (SEG) Si is deposited over the substrate. The spacer is then removed to form an ultra shallow junction in the exposed substrate covered by the spacer after the formation of the SEG Si.

Abstract: CMOS transistors, i.e., N- and P-type transistors, are formed with substantially the same gate length and source/drain regions with lightly doped extensions. Embodiments include sequentially: ion implanting an N-type impurity, e.g. As, to form the N- type transistor shallow source/drain implants; forming relatively thin first sidewall spacers on the gates of both transistors; ion implanting a P-type impurity, e.g. BF2, to form shallow source/drain extension implants for the P-type transistor; forming relatively thick side wall spacers on the first sidewall spacers of both transistors; ion implanting, e.g. As, to form moderately or heavily doped N-type implants; activation annealing at a first temperature, e.g., about 1050° C. to form the shallow N- and P-type source/drain extensions and moderately or heavily doped P-type source/drain regions; ion implanting a P-type impurity, e.g.

Abstract: The present invention provides a method of forming a PMOS transistor or an NMOS transistor on a semiconductor wafer. The semiconductor wafer comprises a silicon substrate and a gate positioned on a predetermined area of the silicon substrate. First, a protection layer of uniform thickness made of silicon nitride is formed on the semiconductor wafer to cover the surface of the gate. Then, a first ion implantation process is performed to form a first ion implantation layer with a first predetermined thickness on the silicon substrate around the gate. Then, an RCA cleaning process is performed to remove impurities on the semiconductor wafer. Next, a spacer is formed around the gate. Finally, a second ion implantation process is performed to form a second ion implantation layer with a second predetermined thickness on the silicon substrate around the gate. The second ion implantation layer is used as a source or drain (S/D) of the MOS transistor.

Abstract: A design for an MOS transistor deliberately uses depletion in a polysilicon gate electrode to improve circuit performance. Conventional transistor design seeks to minimize depletion in a polysilicon gate electrode to increase drive current. According to an embodiment of the present invention, appropriate levels of depletion in the gate electrode, larger than conventional levels, simultaneously provide desired drive current while minimizing circuit delay. According to another aspect, circuit performance is improved by adjusting doping levels in the channel region to maintain a threshold voltage at the same level as that which is achieved with minimum depletion in a polysilicon gate electrode. A method of fabricating an MOS device including a polysilicon gate electrode with increased depletion is also provided.

Abstract: A process for growing an ultra-thin dielelctric layer for use as a MOSFET gate or a tunnel oxide for EEPROM's is described. A silicon oxynitride layer, with peaks in nitrogen concentration at the wafer-oxynitride interface and at the oxynitride surface and with low nitrogen concentration in the oxynitride bulk, is formed by a series of anneals in nitric oxide and nitrous oxide gas. This process provides precise thickness control, improved interface structure, low density electron traps, and impedes dopant impurity diffusion from/to the dielelctric and substrate. The process is easily integrated into existing manufacturing processes, and adds little increased costs.

Abstract: A method of forming a retrograde channel concentration profile in the NMOS region of a semiconductor device and forming a shallow LDD regions in a PMOS region of the semiconductor device. The retrograde channel concentration profile in the NMOS regions is formed by implanting nitrogen and boron ions into the NMOS region at selected concentrations and implantation energy levels. The nitrogen ions are implanted in the NMOS region at a selected concentration in the range of 1×1013 to 2×1015 ions per cm2 and at a selected implantation energy in the range of 10-100 KeV. The boron ions are implanted in the NMOS region at a selected concentration in the range of 1×1012 to 1×1014 ions per cm2 and at a selected implantation energy in the range of 5-50 KeV. The shallow LDD regions in the PMOS region are formed by implanting nitrogen and boron ions into the PMOS region at selected concentrations and implantation energy levels.