Patents by Inventor Ming-Ying Chung

Ming-Ying Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • RTL verification using computational complexity-based property ranking and scheduling
    Patent number: 10521536
    Abstract: A method or apparatus comprising a verification system using a processor to utilize a first set of verification engines to solve easy properties of an integrated circuit design, such as RTL, running a machine-learning algorithm for a hardness ranking analysis on a plurality of properties based on data from the first set of verification engines, and ranking the plurality of properties by a hardness of verification. The method or apparatus further to order the plurality of properties based on the hardness of verification.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: December 31, 2019
    Assignee: Synopsys, Inc.
    Inventors: Jinqing Yu, Manish Pandey, Ming-Ying Chung, Arunava Saha
  • RTL Verification Using Computational Complexity-Based Property Ranking and Scheduling
    Publication number: 20180144071
    Abstract: A method or apparatus comprising a verification system using a processor to utilize a first set of verification engines to solve easy properties of an integrated circuit design, such as RTL, and running a machine-learning algorithm for hardness ranking analysis on a plurality of properties based on data from the first set of verification engines, and ranking the plurality of properties by a hardness of verification. The method of apparatus further to order the plurality of properties based on the hardness of verification.
    Type: Application
    Filed: November 17, 2017
    Publication date: May 24, 2018
    Inventors: Jinqing Yu, Manish Pandey, Ming-Ying Chung, Arunava Saha