Abstract: A display panel comprising a substrate, a plurality of gate lines, source lines, semiconductor layers and light shielding layers is provided. The gate lines are disposed on the substrate in parallel. The source lines are disposed on the substrate in parallel. The gate lines and the source lines are intercrossed to define a plurality of pixel areas. The semiconductor layers are disposed on the corresponding pixel areas, and each semiconductor layer includes at least one channel region overlapping each gate line. The slight shielding layers are located between the channel regions and the substrate. In a normal direction of the substrate, one of the gate lines is overlapped by two of the light shielding layers, and one of the light shielding layers overlaps even number of the source lines.

Abstract: A display panel including a first substrate and a second substrate disposed is provided. The first substrate includes a first data line, a second data line, and a third data line parallel with one another, and a first scan line and a second scan line parallel with each other. The first scan line, the second scan line, the first data line and the second data line define a first sub-pixel. The first scan line, the second scan line, the second data line and the third data line define a second sub-pixel. The first sub-pixel includes a first pixel electrode. The second sub-pixel includes a second pixel electrode. A first interval between the first pixel electrode and the second data line is larger than a second interval between the second pixel electrode and the second data line.

Abstract: A display panel comprising a substrate, a plurality of gate lines, source lines, semiconductor layers and light shielding layers is provided. The gate lines are disposed on the substrate in parallel. The source lines are disposed on the substrate in parallel. The gate lines and the source lines are intercrossed to define a plurality of pixel areas. The semiconductor layers are disposed on the corresponding pixel areas, and each semiconductor layer includes at least one channel region overlapping each gate line. The slight shielding layers are located between the channel regions and the substrate. In a normal direction of the substrate, one of the gate lines is overlapped by two of the light shielding layers, and one of the light shielding layers overlaps even number of the source lines.