Patents by Inventor Ming-Yuan Chuang

Ming-Yuan Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11935871
    Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through silicon via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through silicon via.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Cheng-Chieh Hsieh, Tsung-Hsien Chiang, Hui-Chun Chiang, Tzu-Sung Huang, Ming-Hung Tseng, Kris Lipu Chuang, Chung-Ming Weng, Tsung-Yuan Yu, Tzuan-Horng Liu
  • Publication number: 20230261356
    Abstract: A strip-line structure includes a first ground plane formed on a first layer; a second ground plane formed on a second layer; a first power plane formed on the first layer, wherein the first ground plane and the first power plane are separated by a dielectric material; a stipe line formed on a third layer for signal transmission, wherein the third layer is between the first layer and the second layer; a ground line formed on the third layer, wherein the ground line and the strip line are separated by the dielectric material; a first via for electrically connecting the first ground plane and the second ground plane; and a second via for electrically connecting the ground line and the second ground plane.
    Type: Application
    Filed: April 15, 2022
    Publication date: August 17, 2023
    Applicant: Wistron Corporation
    Inventors: Ming-Yuan Chuang, Sheng-Hsun Tsai, Li-Shang Liu
  • Publication number: 20220020599
    Abstract: Exemplary processing methods may include depositing a boron-containing material or a silicon-and-boron-containing material on a substrate disposed within a processing region of a semiconductor processing chamber. The methods may include etching portions of the boron-containing material or the silicon-and-boron-containing material with a chlorine-containing precursor to form one or more features in the substrate. The methods may also include removing remaining portions of the boron-containing material or the silicon-and-boron-containing material from the substrate with a fluorine-containing precursor.
    Type: Application
    Filed: July 18, 2021
    Publication date: January 20, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Takehito Koshizawa, Karthik Janakiraman, Rui Cheng, Krishna Nittala, Menghui Li, Ming-Yuan Chuang, Susumu Shinohara, Juan Guo, Xiawan Yang, Russell Chin Yee Teo, Zihui Li, Chia-Ling Kao, Qu Jin, Anchuan Wang