Abstract: Methods for forming a gate structure of a multi-gate device are provided. An example method includes depositing a gate dielectric layer over first nanostructures over a first region of a substrate and second nanostructures over a second region of the substrate, depositing a first work function metal (WFM) layer over the first nanostructures and the second nanostructures, depositing a first hard mask (HM) layer over the first WFM layer, selectively removing the first HM layer and the first WFM layer over the first region, selectively removing the first HM layer over the second region, depositing a second WFM layer over the substrate, depositing a second HM layer over the second WFM layer, selectively removing the second HM layer and the second WFM layer over the first region, selectively removing the second HM layer over the second region, and depositing a third WFM layer over the substrate.

Abstract: A semiconductor package includes a semiconductor device, an encapsulating material, a redistribution structure, and an adhesive residue. The encapsulating material encapsulates a first part of a side surface of the semiconductor device. The redistribution structure is disposed over the semiconductor device and a first side of the encapsulating material. The adhesive residue is disposed over a second side of the encapsulating material opposite to the first side and surrounding the semiconductor device, wherein the adhesive residue encapsulates a second part of the side surface of the semiconductor device.

Abstract: A semiconductor device including a semiconductor substrate and an interconnect structure is provided. The semiconductor substrate includes a transistor, wherein the transistor has a source region and a drain region. The interconnect structure is disposed over the semiconductor substrate, wherein the interconnect structure includes a plurality of interlayer dielectric layers, a first via and a memory cell. The plurality of interlayer dielectric layers are over the semiconductor substrate. The first via is embedded in at least two interlayer dielectric layers among the plurality of interlayer dielectric layers and electrically connected with the drain region of the transistor. The memory cell is disposed over the at least two interlayer dielectric layers among the plurality of interlayer dielectric layers and electrically connected with the first via.

Abstract: A digital compute-in-memory (DCIM) macro includes a memory cell array and an arithmetic logic unit (ALU). The memory cell array stores weight data of a neural network. The ALU receives parallel bits of a same input channel in an activation input, and generates a convolution computation output of the parallel bits and target weight data in the memory cell array.

Abstract: A digital compute-in-memory (DCIM) system includes a first DCIM macro. The first DCIM macro includes a first memory cell array and a first arithmetic logic unit (ALU). The first memory cell array has N rows that are configured to store weight data of a neural network in a single weight data download session, wherein N is a positive integer not smaller than two. The first ALU is configured to receive a first activation input, and perform convolution operations upon the first activation input and a single row of weight data selected from the N rows of the first memory cell array to generate first convolution outputs.

Abstract: A method of forming a semiconductor device includes: forming a semiconductor structure having source/drain regions, a fin disposed between the source/drain regions, and a dummy gate disposed on the fin and surrounded by a spacer; removing the dummy gate to form a gate trench which is defined by a trench-defining wall; forming a gate dielectric layer on the trench-defining wall; forming a work function structure on the gate dielectric layer; forming a resist layer to fill the gate trench; removing a top portion of the resist layer; removing the work function structure exposed from the resist layer using a wet chemical etchant; removing the resist layer; and forming a conductive gate in the gate trench.

Abstract: A semiconductor structure includes a first transistor having a first source/drain (S/D) feature and a first gate; a second transistor having a second S/D feature and a second gate; a multi-layer interconnection disposed over the first and the second transistors; a signal interconnection under the first and the second transistors; and a power rail under the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S/D feature and the first gate to one of the second S/D feature and the second gate.

Abstract: A semiconductor fabrication method includes: forming an epitaxial stack including at least one sacrificial epitaxial layer and at least one channel epitaxial layer; forming a plurality of fins in the epitaxial stack; performing tuning operations to prevent a width of the sacrificial epitaxial layer expanding beyond a width of the channel epitaxial layer during operations to form isolation features; forming the isolation features between the plurality of fins, wherein the width of the sacrificial epitaxial layer does not expand beyond the width of the channel epitaxial layer; forming a sacrificial gate stack; forming gate sidewall spacers on sidewalls of the sacrificial gate stack; forming inner spacers around the sacrificial epitaxial layer and the channel epitaxial layer; forming source/drain features; removing the sacrificial gate stack and sacrificial epitaxial layer; and forming a replacement metal gate, wherein the metal gate is shielded from the source/drain features.

Abstract: A semiconductor structure includes a source/drain feature in the semiconductor layer. The semiconductor structure includes a dielectric layer over the source/drain feature. The semiconductor structure includes a silicide layer over the source/drain feature. The semiconductor structure includes a barrier layer over the silicide layer. The semiconductor structure includes a seed layer over the barrier layer. The semiconductor structure includes a metal layer between a sidewall of the seed layer and a sidewall of the dielectric layer, a sidewall of each of the silicide layer, the barrier layer, and the metal layer directly contacting the sidewall of the dielectric layer. The semiconductor structure includes a source/drain contact over the seed layer.

Abstract: A non-volatile memory device includes a substrate, a stacked structure, an anti-fuse gate, a gate dielectric layer, a first doping region, and a second doping region. The stacked structure is formed on the substrate and includes a floating gate, a select logic gate, a logic gate dielectric layer, and an inter-polysilicon layer dielectric layer. The select logic gate is disposed on the floating gate, the logic gate dielectric layer is disposed between the floating gate and the substrate, and the inter-polysilicon layer dielectric layer is disposed between the floating gate and the select logic gate. The anti-fuse gate is disposed on the substrate, and the gate dielectric layer is disposed between the anti-fuse gate and the substrate. The first doping region is formed in the substrate at one side of the floating gate. The second doping region is formed in the substrate between the floating gate and the anti-fuse gate.

Abstract: A modular assembly of an endoscope light source and an image-capturing module includes: a circuit board having a lower plate and an elevation support platform located on the top surface of the lower plate and having a predefined height, a bottom surface of the lower plate having a plurality of bottom electrode sheets disposed thereon, a top end of the elevation support platform having a plurality of light source electrode sheets disposed thereon, the plurality of light source electrode sheets using a plurality of lead wires to penetrate through the elevation support platform and the lower plate in order to be electrically connected to the plurality of bottom electrode sheets; a plurality of light emitting diode chips having a florescent powder gel covered thereon; an image-capturing module; and a fixation glue cured and attached onto the image-capturing module, the elevation support platform and the fluorescent powder gel.

Abstract: A non-volatile memory device includes a substrate, a stacked structure, an anti-fuse gate, a gate dielectric layer, a first doping region, and a second doping region. The stacked structure is formed on the substrate and includes a floating gate, a select logic gate, a logic gate dielectric layer, and an inter-polysilicon layer dielectric layer. The select logic gate is disposed on the floating gate, the logic gate dielectric layer is disposed between the floating gate and the substrate, and the inter-polysilicon layer dielectric layer is disposed between the floating gate and the select logic gate. The anti-fuse gate is disposed on the substrate, and the gate dielectric layer is disposed between the anti-fuse gate and the substrate. The first doping region is formed in the substrate at one side of the floating gate. The second doping region is formed in the substrate between the floating gate and the anti-fuse gate.

Abstract: An endoscope tubing includes: a picture-taking component defined with a front end and a rear end and having an image-capturing lens disposed at the front end to capture images forward, a light source and an outer wall, with the light source disposed at a rim of the image-capturing lens to illuminate, and the outer wall being circular and protruding toward the front of the picture-taking component to form a protruding dam; a spring tube with an end connected to the rear end of the picture-taking component and another end connected to a predetermined device; a tensile cable with a portion thereof connected to the picture-taking component and another portion thereof passing through the spring tube to connect to the predetermined device; and a wire with an end connected to the picture-taking component and another end passing through the spring tube to connect to the predetermined device.

Abstract: A camera module includes a lens holder, a lens module, an image sensor chip, and a printed circuit board. The lens module is received in the lens holder. The lens module includes a lens barrel and at least one lens received in the lens barrel. The image sensor chip has a photosensitive area configured for receiving light transmitted through the lens module. The printed circuit board defines a top surface for receiving both the image sensor chip and the lens barrel thereon and an opposite bottom surface thereon. The bottom surface defines a plurality of recesses thereon for receiving the corresponding electronic elements therein by adhesives.

Abstract: A camera module includes a lens assembly and a baseboard assembly mounted on the lens assembly. The lens assembly includes a lens, a barrel receiving the lens, and a support receiving the barrel. The baseboard assembly includes a circuit board and an image sensor on the circuit board. The support defines a clamping recess at an outer surface thereof.

Abstract: A camera module includes a lens holder, a lens module, an image sensor chip, and a printed circuit board. The lens module is received in the lens holder. The lens module includes a lens barrel and at least one lens received in the lens barrel. The image sensor chip has a photosensitive area configured for receiving light transmitted through the lens module. The printed circuit board defines a top surface for receiving both the image sensor chip and the lens barrel thereon and an opposite bottom surface thereon. The bottom surface defines a plurality of recesses thereon for receiving the corresponding electronic elements therein by adhesives.

Abstract: A camera module includes a lens assembly and a baseboard assembly mounted on the lens assembly. The lens assembly includes a lens, a barrel receiving the lens, and a support member receiving the barrel. The baseboard assembly includes a circuit board and an image sensor on the circuit board. The baseboard defines a friction surface at a side surface thereof.

Abstract: A camera module includes a lens assembly and a baseboard assembly mounted on the lens assembly. The lens assembly includes a lens, a barrel receiving the lens, and a support receiving the barrel. The baseboard assembly includes a circuit board and an image sensor on the circuit board. The support defines a clamping recess at an outer surface thereof.

Abstract: A camera module includes a lens assembly and a baseboard assembly mounted on the lens assembly. The lens assembly includes a lens, a barrel receiving the lens, and a support member receiving the barrel. The baseboard assembly includes a circuit board and an image sensor on the circuit board. The baseboard defines a friction surface at a side surface thereof.

Abstract: A camera module includes a lens holder, a lens module, an image sensor chip, and a PCB defining a step-shaped recess on the upper thereof. The step-shaped recess comprises a first recess formed on an upper portion thereof and a second recess, for receiving a plurality of electrical elements therein, coaxially formed on a lower portion thereof, and a intermediate step surface formed between the first recess and the second recess. A cover plate received in the first recess and attached on the intermediate step surface defines at least one electronic layer therein and an external point formed on the bottom thereof. At least one zero voltage point is formed on the intermediate step surface thereof. The electronic layer is electrically connected to the zero voltage points by the external points, thereby electromagnetic waves generated by the electronic elements are prevented from affecting the image sensor chip.