Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.

Abstract: In some implementations, one or more semiconductor processing tools may form a via within a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a ruthenium-based liner within the via. The one or more semiconductor processing tools may deposit, after depositing the ruthenium-based liner, a copper plug within the via.

Abstract: Memory stacks, memory devices and method of forming the same are provided. A memory stack includes a spin-orbit torque layer, a magnetic bias layer and a free layer. The magnetic bias layer is in physical contact with the spin-orbit torque layer and has a first magnetic anisotropy. The free layer is disposed adjacent to the spin-orbit torque layer and has a second magnetic anisotropy perpendicular to the first magnetic anisotropy.

Abstract: The present disclosure provides an immersion cooling system for a server cabinet including a plurality of server boxes, a cooling tank and a plurality of liquid connecting pipes. Each server box includes an electronic device immersed in the cooling liquid, and the electronic device generates a thermal energy so that part of the cooling liquid evaporates into a hot vapor. The cooling tank is connected to the plurality of server boxes and includes a condenser and a storage part. The condenser is connected to each server box and condenses the hot vapor to form the cooling liquid. The storage part storages the cooling liquid from the condenser. Two ends of the liquid connecting pipe is connected to the storage part and the server box respectively. The cooling liquid in the storage part and the cooling liquid of each server box are maintained in a same liquid level.

Abstract: A method of forming a semiconductor device includes forming a first epitaxial layer over a substrate to form a wafer, depositing a dielectric layer over the first epitaxial layer, patterning the dielectric layer to form an opening, etching the first epitaxial layer through the opening to form a recess, forming a second epitaxial layer in the recess, etching the dielectric layer to expose a top surface of the first epitaxial layer, and planarizing the exposed top surface of the first epitaxial layer and a top surface of the second epitaxial layer.

Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming a source/drain region over the fin adjacent to the gate structure; forming an interlayer dielectric (ILD) layer over the source/drain region around the gate structure; forming an opening in the ILD layer to expose the source/drain region; forming a silicide region and a barrier layer successively in the openings over the source/drain region, where the barrier layer includes silicon nitride; reducing a concentration of silicon nitride in a surface portion of the barrier layer exposed to the opening; after the reducing, forming a seed layer on the barrier layer; and forming an electrically conductive material on the seed layer to fill the opening.

Abstract: A method of forming a semiconductor device includes forming a first epitaxial layer over a substrate to form a wafer, depositing a dielectric layer over the first epitaxial layer, patterning the dielectric layer to form an opening, etching the first epitaxial layer through the opening to form a recess, forming a second epitaxial layer in the recess, etching the dielectric layer to expose a top surface of the first epitaxial layer, and planarizing the exposed top surface of the first epitaxial layer and a top surface of the second epitaxial layer.

Abstract: A reticle includes a border section surrounding a pattern section, and gas openings arranged in and passing through the border section. The gas openings are coupled to a gas supply. Each gas opening extends in a first direction inclined to and forming an angle with a reticle center axis that extends perpendicularly away from a front surface of the reticle, and is configured to blow a pressurized gas in the first direction away from the front surface to create an air wall adjacent to and surrounding the front surface, thereby advantageously preventing particles from falling on the front surface of the reticle.

Abstract: A fan management system includes a fan and a server. The fan includes a driving circuit, and the driving circuit is configured for driving the fan. The fan operates in an operation mode. The server is connected to the fan and is configured for controlling the operation of the fan. The driving circuit outputs a digital label signal when the fan operates abnormally, and the server obtains a production history, an operation information and a warning message of the fan through the digital label signal. The server adjusts the operation mode of the fan according to the warning message simultaneously.

Abstract: A device includes a first circuit region including a nanostructure device and a second circuit region offset from the first circuit region. The nanostructure device has a vertical stack of nanostructures disposed in a plurality of first semiconductor layers and a gate structure wrapping around the nanostructures of the vertical stack. The second circuit region includes a bipolar junction device electrically connected to the nanostructure device and at least one diode electrically connected between a collector and a base of the bipolar junction device. At least one implant region extends through the plurality of first semiconductor layers and a plurality of second semiconductor layers that are disposed between respective vertically neighboring pairs of the plurality of first semiconductor layers. A backside interconnect structure is electrically connected to a source/drain region of the nanostructure device.

Abstract: Mechanism of relay UE discovery and relay UE selection and reselection for remote UE data transmission with a serving base station via relay UE is proposed. A method operable for relay UE selection and reselection of remote UE is provided. The UE considers additional criteria such as relay load other than purely radio signal quality (e.g., RSRP) criteria. The relay load can serve different purpose for relay UE and remote UE. The relay load can be the criteria for UE to become a relay UE or not. It can be the criteria for a remote UE to select another UE as its relay UE.

Abstract: A method of forming a semiconductor device includes forming a CFET structure having a bottom gate region having a first plurality of gate dielectric layers wrapping around a first plurality of channels and a top gate region having a second plurality of gate dielectric layers wrapping around a second plurality of channels. The method includes performing a first dipole loop process to drive first dipole dopants into the first plurality of gate dielectric layers and performing a second dipole loop process to drive second dipole dopants into the second plurality of gate dielectric layers. And after performing the first and second dipole loop processes, the method includes depositing a gate metal over the first and second plurality of gate dielectric layers.

Abstract: A semiconductor device includes a substrate. The semiconductor device includes a dielectric fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate isolation structure vertically disposed above the dielectric fin. The semiconductor device includes a gate structure extending along a second direction perpendicular to the first direction. The gate structure includes a first portion and a second portion separated by the gate isolation structure and the dielectric fin. The first portion of the gate structure presents a first beak profile and the second portion of the gate structure presents a second beak profile. The first and second beak profiles point toward each other.

Abstract: A light box structure includes a bracket and a board. The bracket is in an arc shape and has a first surface and a second surface opposite to each other. The board has a plurality of magnetic positioning posts. The magnetic positioning posts have at least two different heights. The board is attracted and attached on the first surface of the bracket through the magnetic positioning posts.

Abstract: In some implementations, one or more semiconductor processing tools may form a via within a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a ruthenium-based liner within the via. The one or more semiconductor processing tools may deposit, after depositing the ruthenium-based liner, a copper plug within the via.

Abstract: A semiconductor device includes a semiconductor fin. The semiconductor device includes a metal gate disposed over the semiconductor fin. The semiconductor device includes a gate dielectric layer disposed between the semiconductor fin and the metal gate. The semiconductor device includes first spacers sandwiching the metal gate. The first spacers have a first top surface and the gate dielectric layer has a second top surface, and the first top surface and a first portion of the second top surface are coplanar with each other. The semiconductor device includes second spacers further sandwiching the first spacers. The second spacers have a third top surface above the first top surface and the second top surface. The semiconductor device includes a gate electrode disposed over the metal gate.

Abstract: The present invention provides a sensor circuit with noise elimination comprising: a reference circuit which receives plural first sensing signals and generates a ramp signal based on the first sensing signal; and a comparison circuit which is coupled to the reference circuit, and which receives a second sensing signal and a ramp signal and generates a count signal based on the ramp signal and the second sensing signal and records the count signal at the time when the ramp signal is equal to the second sensing signal, thereby eliminating the noise of the second sensing signal to obtain a noise-free sensing value. The count signal is recorded when the ramp signal and the second sense signal are equal, so that the noise of the second sense signal is eliminated and a noise-free sense value is obtained.

Abstract: An image recognition method includes the steps of: receiving a captured image; acquiring a focusing zone image from a portion of the captured image; processing the captured image and/or the focusing zone image and then making the two images into a batch of image information; and executing an image analysis procedure on the batch of image information to generate an analysis result.

Abstract: An image processing circuit performs super-resolution (SR) operations. The image processing circuit includes memory to store multiple parameter sets of multiple artificial intelligence (AI) models. The image processing circuit further includes an image guidance module, a parameter decision module, and an SR engine. The image guidance module operates to detect a representative feature in an image sequence including a current frame and past frames within a time window. The parameter decision module operates to adjust parameters of one or more AI models based on a measurement of the representative feature. The SR engine operates to process the current frame using the one or more AI models with the adjusted parameters to thereby generate a high-resolution image for display.