Patents by Inventor Ming-Yuan Wu

Ming-Yuan Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240098125
    Abstract: The present disclosure relates to a system, a method and a computer-readable medium for rendering a streaming on a user terminal. The method includes rendering the streaming in a first mode, receiving an environment parameter of the user terminal, receiving a timing when the user terminal closes the streaming, determining a threshold value of the environment parameter based on the timing the user terminal closes the streaming, receiving an updated environment parameter of the user terminal, and rendering the streaming in a second mode if the updated environment parameter meets the threshold value. The second mode includes fewer data objects than the first mode or includes a downgraded version of a data object in the first mode for the rendering. The present disclosure can customize the rendering mode for each user and maximize the satisfaction of viewing streaming for each user.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Yung-Chi HSU, Chung-Chiang HSU, Shao-Yuan WU, Ming-Che CHENG, Ka Chon LOI
  • Publication number: 20240094362
    Abstract: A point cloud positioning error detection method, performed by a processing device, includes: obtaining a plurality of pieces of first point data and a target point cloud map, wherein the target point cloud map includes a plurality of pieces of target point data, registering the first point data and the target point data to obtain a plurality of pieces of second point data, selecting a plurality of pieces of third point data from the second point data according to a first default distance, calculating a plurality of matching scores of the third point data relative to the target point data, obtaining a plurality of step vectors corresponding to the third point data, respectively, when said registering converges, and obtaining a plurality of effective values according to directions of the step vectors, and outputting a localization fault detection result based on an intersection of the matching scores and the effective values.
    Type: Application
    Filed: December 27, 2022
    Publication date: March 21, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Wei-Yuan HSIEH, Ming-Xuan WU, Chia-Jui HU
  • Patent number: 11929767
    Abstract: A transmission interface between at least a first module and a second module is proposed. The transmission interface includes at least two physical transmission mediums. Each physical transmission medium is arranged to carry a multiplexed signal in which at least two signals are integrated. The at least two physical transmission mediums include a first physical transmission medium arranged to carry a first multiplexed signal including a first IF signal and a reference clock signal. The first IF signal and the reference clock signal are at different frequencies.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: March 12, 2024
    Assignee: MEDIATEK INC.
    Inventors: Chieh-Hsun Hsiao, Ming-Chou Wu, Wen-Chang Lee, Narayanan Baskaran, Wei-Hsin Tseng, Jenwei Ko, Po-Sen Tseng, Hsin-Hung Chen, Chih-Yuan Lin, Caiyi Wang
  • Patent number: 11913981
    Abstract: An electrostatic sensing system configured to sense an electrostatic information of a fluid inside a fluid distribution component and including an electrostatic sensing assembly, a signal amplifier and an analog-to-digital converter. The electrostatic sensing assembly includes a sensing component, and a shield. The sensing component is configured to be disposed at the fluid distribution component. The sensing component is disposed through the fluid distribution component so as to be partially located in the fluid distribution component. The shield surrounds a part of the sensing component that is located in the fluid distribution component. At least part of the shield is located on an upstream side of the sensing component. The signal amplifier is electrically connected to the sensing component. The analog-to-digital converter is electrically connected to the signal amplifier. The shield has an opening spaced apart from the sensing component.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: February 27, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Mean-Jue Tung, Ming-Da Yang, Shi-Yuan Tong, Yu-Ting Huang, Chun-Pin Wu
  • Publication number: 20230395436
    Abstract: Semiconductor devices and methods are provided. In an embodiment, a method includes providing a workpiece including a first hard mask layer on a top surface of a substrate, performing an ion implantation process to form a doped region in the substrate, after the performing of the ion implantation process, annealing the workpiece at temperature T1. The method also includes selectively removing the first hard mask layer, after the selectively removing of the first hard mask layer, performing a pre-bake process at temperature T2, and, after the performing of the pre-bake process, epitaxially growing a vertical stack of alternating channel layers and sacrificial layers on the substrate, where the temperature T2 is lower than the temperature T1.
    Type: Application
    Filed: June 7, 2022
    Publication date: December 7, 2023
    Inventors: Ming-Yuan Wu, Ka-Hing Fung, Min Jiao, Da-Wen Lin, Wei-Yuan Jheng
  • Publication number: 20230137528
    Abstract: The present disclosure provides a method that includes providing a substrate including a first circuit region and a second circuit region; forming a semiconductor stack on the substrate, wherein the semiconductor stack includes first semiconductor layers of a first composition and second semiconductor layers of a second composition alternatively stacked on the substrate; performing a first patterning process to the semiconductor stack and the substrate to form first trenches having a first depth; and performing a second patterning process to the semiconductor stack and the substrate, thereby forming second trenches of a second depth in the first circuit region and third trenches of a third depth in the second circuit region, the third depth being less than the second depth.
    Type: Application
    Filed: June 4, 2022
    Publication date: May 4, 2023
    Inventors: Ming-Yuan Wu, Min Jiao, Da-Wen Lin
  • Patent number: 11616133
    Abstract: A method includes forming a doped region on a top portion of a substrate, forming a first epitaxial layer over the substrate, forming a recess in the first epitaxial layer, the recess being aligned to the doped region, performing a surface clean treatment in the recess, the surface clean treatment includes: oxidizing surfaces of the recess to form an oxide layer in the recess, and removing the oxide layer from the surfaces of the recess, and forming a second epitaxial layer in the recess.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: March 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Lun Chang, Shiao-Shin Cheng, Ji-Yin Tsai, Yu-Lin Tsai, Hsin-Chieh Huang, Ming-Yuan Wu, Jiun-Ming Kuo, Ming-Jie Huang, Yu-Wen Wang, Che-Yuan Hsu
  • Publication number: 20230015372
    Abstract: A method includes forming a fin protruding from a substrate, forming a first dielectric feature adjacent to the fin over the substrate, forming a cladding layer over the fin and the first dielectric feature, and removing a portion of the cladding layer to form an opening. The opening exposes the first dielectric feature. The method further includes forming a second dielectric feature adjacent to the cladding layer, the second dielectric feature filling the opening, forming a dummy gate stack over the fin and the second dielectric feature, forming source/drain (S/D) features in the fin adjacent to the dummy gate stack, and replacing the dummy gate stack and the cladding layer with a metal gate stack. The second dielectric feature divides the metal gate stack.
    Type: Application
    Filed: May 4, 2022
    Publication date: January 19, 2023
    Inventors: Ming-Yuan Wu, Da-Wen Lin, Yi-Ting Fu, Hsu-Chieh Cheng, Min Jiao
  • Publication number: 20220367200
    Abstract: A method of forming a semiconductor device includes forming a first epitaxial layer over a substrate to form a wafer, depositing a dielectric layer over the first epitaxial layer, patterning the dielectric layer to form an opening, etching the first epitaxial layer through the opening to form a recess, forming a second epitaxial layer in the recess, etching the dielectric layer to expose a top surface of the first epitaxial layer, and planarizing the exposed top surface of the first epitaxial layer and a top surface of the second epitaxial layer.
    Type: Application
    Filed: June 20, 2022
    Publication date: November 17, 2022
    Inventors: Che-Lun Chang, Pin-Chuan Su, Hsin-Chieh Huang, Ming-Yuan Wu, Tzu kai Lin, Yu-Wen Wang, Che-Yuan Hsu
  • Publication number: 20220262926
    Abstract: A method includes forming a doped region on a top portion of a substrate, forming a first epitaxial layer over the substrate, forming a recess in the first epitaxial layer, the recess being aligned to the doped region, performing a surface clean treatment in the recess, the surface clean treatment includes: oxidizing surfaces of the recess to form an oxide layer in the recess, and removing the oxide layer from the surfaces of the recess, and forming a second epitaxial layer in the recess.
    Type: Application
    Filed: April 25, 2022
    Publication date: August 18, 2022
    Inventors: Che-Lun Chang, Shiao-Shin Cheng, Ji-Yin Tsai, Yu-Lin Tsai, Hsin-Chieh Huang, Ming-Yuan Wu, Jiun-Ming Kuo, Ming-Jie Huang, Yu-Wen Wang, Che-Yuan Hsu
  • Patent number: 11387109
    Abstract: A method of forming a semiconductor device includes forming a first epitaxial layer over a substrate to form a wafer, depositing a dielectric layer over the first epitaxial layer, patterning the dielectric layer to form an opening, etching the first epitaxial layer through the opening to form a recess, forming a second epitaxial layer in the recess, etching the dielectric layer to expose a top surface of the first epitaxial layer, and planarizing the exposed top surface of the first epitaxial layer and a top surface of the second epitaxial layer.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: July 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Lun Chang, Pin-Chuan Su, Hsin-Chieh Huang, Ming-Yuan Wu, Tzu kai Lin, Yu-Wen Wang, Che-Yuan Hsu, deseased
  • Patent number: 11316030
    Abstract: A method includes forming a doped region on a top portion of a substrate, forming a first epitaxial layer over the substrate, forming a recess in the first epitaxial layer, the recess being aligned to the doped region, performing a surface clean treatment in the recess, the surface clean treatment includes: oxidizing surfaces of the recess to form an oxide layer in the recess, and removing the oxide layer from the surfaces of the recess, and forming a second epitaxial layer in the recess.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: April 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Lun Chang, Shiao-Shin Cheng, Ji-Yin Tsai, Yu-Lin Tsai, Hsin-Chieh Huang, Ming-Yuan Wu, Jiun-Ming Kuo, Ming-Jie Huang, Yu-Wen Wang, Che-Yuan Hsu
  • Publication number: 20220009693
    Abstract: A composite board structure and a box structure. According to the composite board structure, by using through holes (214) and pits (21), under the condition of greatly reducing the material and manufacturing costs, the structural performance of the board is improved, and the bending strength of the board is improved, so that the board can replace the existing boards such as corrugated paper, can be applied to structures such as a box, can replace the existing board and box structures under the condition of greatly reducing the material and manufacturing costs, can also be repeatedly used, and has great contribution to environmental protection and related industries.
    Type: Application
    Filed: November 13, 2019
    Publication date: January 13, 2022
    Inventor: Ming-Yuan WU
  • Publication number: 20210257479
    Abstract: A method includes forming a doped region on a top portion of a substrate, forming a first epitaxial layer over the substrate, forming a recess in the first epitaxial layer, the recess being aligned to the doped region, performing a surface clean treatment in the recess, the surface clean treatment includes: oxidizing surfaces of the recess to form an oxide layer in the recess, and removing the oxide layer from the surfaces of the recess, and forming a second epitaxial layer in the recess.
    Type: Application
    Filed: September 15, 2020
    Publication date: August 19, 2021
    Inventors: Che-Lun Chang, Shiao-Shin Cheng, Ji-Yin Tsai, Yu-Lin Tsai, Hsin-Chieh Huang, Ming-Yuan Wu, Jiun-Ming Kuo, Ming-Jie Huang, Yu-Wen Wang, Che-Yuan Hsu
  • Patent number: 10707331
    Abstract: A method includes forming a fin structure on a substrate, forming a dummy gate structure wrapped around the fin structure, depositing an Interlayer Dielectric (ILD) layer over the fin structure, removing the dummy gate structure to expose a portion of the fin structure, and performing an etching process on the portion of the fin structure to reduce a width of the portion of the fin structure.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: July 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ka-Hing Fung, Chen-Yu Hsieh, Che-Yuan Hsu, Ming-Yuan Wu, Hsu-Chieh Cheng
  • Publication number: 20180315837
    Abstract: A method includes forming a fin structure on a substrate, forming a dummy gate structure wrapped around the fin structure, depositing an Interlayer Dielectric (ILD) layer over the fin structure, removing the dummy gate structure to expose a portion of the fin structure, and performing an etching process on the portion of the fin structure to reduce a width of the portion of the fin structure.
    Type: Application
    Filed: April 28, 2017
    Publication date: November 1, 2018
    Inventors: Ka-Hing Fung, Chen-Yu Hsieh, Che-Yuan Hsu, Ming-Yuan Wu, Hsu-Chieh Cheng
  • Patent number: 10028571
    Abstract: A backpack structure is adapted to provide a storage space, and integrated with a tent structure. The backpack body has a right connection portion and a left connection portion to connect the left sidewall and the right sidewall, wherein the connections are pins, buttons, strips or velcros. The tent structure is stored in the compartment of the backpack body, or the left sidewall and the right sidewall. The tent structure includes a tent base, a left tent portion and a right tent portion. The compartment may has pads, made of cushioning materials, such as foam, to replace the camping mat, for rest. Therefore, the backpack structure of the invention is light for the users of outdoor activities. Moreover, the backpack structure may combine with a trolley structure for drawing easily, or the backpack structure may be designed as a luggage suitcase.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: July 24, 2018
    Inventor: Ming-Yuan Wu
  • Patent number: 9917088
    Abstract: A device comprises a substrate comprising a first portion and a second portion separated by an isolation region, a first gate structure over the first portion, a first drain/source region and a second drain/source region in the first portion and on opposite sides of the first gate structure, wherein the first drain/source region and the second drain/source have concave surfaces, a second gate structure over the second portion and a third drain/source region and a fourth drain/source region in the second portion and on opposite sides of the second gate structure, wherein the third drain/source region and the fourth drain/source have the concave surfaces.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: March 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Yuan Wu, Yen-Po Lin, Yu-Shan Lu, Che-Yuan Hsu
  • Publication number: 20180028017
    Abstract: A grill pan structure with convection heating is provided to make uniformly heating within the oven. The grill pan structure includes a heat flow layer and at least one support plate. The heat flow layer includes at least one hole for a heat source to pass through for roasting. Also, the heat flow layer includes at least one recess to receive the dropped oils of the foods during roasting. The first support plate further includes at least one inclined guiding surface to guide the dropped oil to the recess. Therefore, uniformly heating for roasting foods and eliminate from turning over the foods during roasting are achieved. And the oven is still clean after roasting, which is convenient to use.
    Type: Application
    Filed: July 26, 2016
    Publication date: February 1, 2018
    Inventor: Ming-Yuan WU
  • Publication number: 20170112267
    Abstract: A backpack structure is adapted to provide a storage space, and integrated with a tent structure. The backpack body has a right connection portion and a left connection portion to connect the left sidewall and the right sidewall, wherein the connections are pins, buttons, strips or velcros. The tent structure is stored in the compartment of the backpack body, or the left sidewall and the right sidewall. The tent structure includes a tent base, a left tent portion and a right tent portion. The compartment may has pads, made of cushioning materials, such as foam, to replace the camping mat, for rest. Therefore, the backpack structure of the invention is light for the users of outdoor activities. Moreover, the backpack structure may combine with a trolley structure for drawing easily, or the backpack structure may be designed as a luggage suitcase.
    Type: Application
    Filed: July 13, 2016
    Publication date: April 27, 2017
    Inventor: Ming-Yuan Wu