Patents by Inventor Mingyuan Xu
Mingyuan Xu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11848062Abstract: A voltage control method and a voltage control circuit for an anti-fuse memory array, including: obtaining a storage data address, dividing the storage data address into multiple subdata addresses, decoding each subdata address to obtain a corresponding group of decoder output signals, converting the corresponding group of decoder output signals into a group of control signals by a corresponding group of high voltage converters; connecting multiple groups of data selectors in series, outputting selection voltages input to each group of data selectors to an anti-fuse unit under the control of the corresponding group of control signals; programming or reading an anti-fuse unit; the selection voltages include one of a programming selection voltage, a reading selection voltage, and a non-designated selection voltage. The present disclosure reduces the number of transistors and saves layout areas when the programming or reading operation is performed.Type: GrantFiled: September 1, 2020Date of Patent: December 19, 2023Assignee: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATIONInventors: Yan Wang, Peijian Zhang, Mingyuan Xu, Xian Chen, Feiyu Jiang, Xiyi Liao, Sheng Qiu, Zhengyuan Zhang, Ruzhang Li, Hequan Jiang, Yonghong Dai
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Publication number: 20230197178Abstract: A voltage control method and a voltage control circuit for an anti-fuse memory array, including: obtaining a storage data address, dividing the storage data address into multiple subdata addresses, decoding each subdata address to obtain a corresponding group of decoder output signals, converting the corresponding group of decoder output signals into a group of control signals by a corresponding group of high voltage converters; connecting multiple groups of data selectors in series, outputting selection voltages input to each group of data selectors to an anti-fuse unit under the control of the corresponding group of control signals; programming or reading an anti-fuse unit; the selection voltages include one of a programming selection voltage, a reading selection voltage, and a non-designated selection voltage. The present disclosure reduces the number of transistors and saves layout areas when the programming or reading operation is performed.Type: ApplicationFiled: September 1, 2020Publication date: June 22, 2023Applicant: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATIONInventors: Yan WANG, Peijian ZHANG, Mingyuan XU, Xian CHEN, Feiyu JIANG, Xiyi LIAO, Sheng QIU, Zhengyuan ZHANG, Ruzhang LI, Hequan JIANG, Yonghong DAI
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Patent number: 11502657Abstract: A clock driver circuit, including: an input stage, a double-ended to single-ended conversion stage and a driver output stage connected in sequence. The input stage includes two mutually loaded differential amplifiers and a common mode negative feedback loop. The differential amplifiers are connected to a differential clock signal for amplification to generate a common mode voltage. The common mode feedback circuit is connected to an output end of the differential amplifiers to stabilize the output amplitude of the common mode voltage. The double-ended to single-ended conversion stage converts a differential sine clock signal output by the double-ended common mode voltage into a single-ended square wave clock signal. The driver output stage includes a multi-stage cascaded push-pull phase inverter to improve the drive capability of the square wave clock signal.Type: GrantFiled: July 25, 2018Date of Patent: November 15, 2022Assignee: NO. 24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATIONInventors: Xiaofeng Shen, Xingfa Huang, Liang Li, Xi Chen, Mingyuan Xu, Jian'an Wang, Dongbing Fu, Guangbing Chen
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Publication number: 20220323817Abstract: Disclosed is a structurally simple, easy assembled and multifunctional kettlebell. The kettlebell comprises a kettlebell body. The kettlebell body is provided with a counterweight groove for placing at least one counterweight. The kettlebell body is provided with a positioning cover for positioning the counterweight within the kettlebell body. The positioning cover is detachably mounted in the counterweight groove. The positioning cover is capable of being raised and lowered on the kettlebell body for positioning each counterweight.Type: ApplicationFiled: May 17, 2021Publication date: October 13, 2022Inventor: Mingyuan Xu
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Patent number: 11404371Abstract: The present disclosure provides a one-time programmable capacitive fuse bit, including an upper plate, the upper plate includes a plurality of fuses arranged side by side and spaced by an internal from each other, middle portions of two adjacent fuses are connected to each other; a connecting portion connected to the fuse is disposed above two ends and the middle portion of each of the plurality of fuses; the fuse bit further includes a lower plate corresponding to the two ends and the middle portion of the fuse, the lower plate is disposed below the fuse; the lower plate corresponding to the middle portion of the fuse is opposite to the connecting portion corresponding to the middle portion of the fuse; a hollow portion is disposed between the lower plate corresponding to the middle portion of the fuse and the lower plate corresponding to both ends of the fuse.Type: GrantFiled: July 18, 2018Date of Patent: August 2, 2022Assignee: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATIONInventors: Mingyuan Xu, Shuiqin Yao, Liang Li, Xiaofeng Shen, Hongrui Yang, Jian'an Wang, Dongbing Fu, Guangbing Chen, Xingfa Huang, Xi Chen
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Publication number: 20220226688Abstract: Disclosed is a simple and convenient multifunctional exercise apparatus allowing users to do varies exercise. The exercise apparatus comprises a support board, and a plurality of support rods are provided on the support board to support the support board. A plurality of grip rods are arranged between the support rods for doing push-ups.Type: ApplicationFiled: March 26, 2021Publication date: July 21, 2022Inventor: Mingyuan XU
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Patent number: 11353505Abstract: The present disclosure provides a differential clock cross point detection circuit and a detection method. The detection circuit includes: a first MOS transistor (M1), a second MOS transistor (M2) and a capacitor (C); a drain of the first MOS transistor (M1) is connected to a negative terminal (CLK?) of a differential clock, a gate of the first MOS transistor (M1) is connected to a positive terminal (CLK+) of the differential clock, and a source of the first MOS transistor (M1) is connected to a drain of the second MOS transistor (M2); a gate of the second MOS transistor (M2) is connected to the negative terminal (CLK?) of the differential clock, and a source of the second MOS transistor (M2) is connected to an output terminal through a node; one terminal of the capacitor (C) is connected to a node (A), and the other terminal of the capacitor (C) is grounded.Type: GrantFiled: January 7, 2020Date of Patent: June 7, 2022Assignees: NO. 24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION, CHONGQING GIGACHIP TECHNOLOGY CO. LTD.Inventors: Mingyuan Xu, Liang Li, Jun Liu, Xiaofeng Shen, Jianan Wang, Dongbing Fu, Guangbing Chen, Xingfa Huang, Xi Chen
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Publication number: 20220168612Abstract: The present application provides a wrist strength training device which is mainly aimed at wrist strength training and is very safe to use, including a threaded rod, a resistance member sheathed on the threaded rod and a torsion handle sheathed on both ends of the threaded rod and connected with the threaded rod, the resistance member is arranged between the two torsion handles on the threaded rod.Type: ApplicationFiled: May 25, 2021Publication date: June 2, 2022Inventor: Mingyuan Xu
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Patent number: 11323129Abstract: The present disclosure provides a circuit for generating a multi-phase clock having random disturbance added thereto. The circuit for generating a clock includes a main clock module, a random signal generation module and a buffer matrix switch module. The main clock module generates N multi-phase clock signals; and the buffer matrix switch module randomly switches, under the control of a random control signal output by the random signal generation module, transmission paths of the input N multi-phase clock signals, and outputs N multi-phase clock signals with random disturbance. In the present disclosure, the clock phase error is whitened by adding random disturbance. Only with a small loss of signal-to-noise ratio, the influence of a multi-phase clock phase error on the performance of a high-precision TI ADC can be eliminated in real time, and the influence of the fluctuation of a clock phase error can be tracked and eliminated.Type: GrantFiled: December 13, 2018Date of Patent: May 3, 2022Assignee: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATIONInventors: Jie Pu, Gangyi Hu, Dongbing Fu, Zhengping Zhang, Liang Li, Ting Li, Daiguo Xu, Mingyuan Xu, Xiaofeng Shen, Xianjie Wan, Youhua Wang
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Publication number: 20220117591Abstract: An adsorption head includes a body. The body is a hollow housing, one side of the housing to which an adsorbed object is adsorbed is provided with an opening. The body comprises at least one adsorption chamber and at least one operation chamber therein, wherein the operation chamber and the adsorption chamber are spaced from each other and each have an opening orientated to the adsorbed object. The body has at least one adsorption passage and at least one operation passage thereon, wherein one end of the adsorption passage is communicated with the adsorption chamber, and one end of the operation passage is communicated with the operation chamber.Type: ApplicationFiled: December 27, 2021Publication date: April 21, 2022Applicant: DEKE MEDTECH (HANGZHOU) INC.Inventors: Nan SHAO, Zhiming WU, Zhenjun ZI, Jingjing HU, Mingyuan XU
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Publication number: 20220111242Abstract: The application provides a yoga tension ring for fitness use, including a tension ring body, the two sides of the yoga tension ring which are in contact with the human body will not curl due to the stretching during the fitness use of stride, buttock bridge, thigh, buttock, up and down squat, lateral movement, etc., and the side of the tension loop body in contact with the human body is detachably provided with an anti-curling device for preventing the curling of the two sides of the tension loop body due to stretching during movement.Type: ApplicationFiled: May 26, 2021Publication date: April 14, 2022Inventors: Linlin Li, Mingyuan Xu
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Patent number: 11290091Abstract: The present disclosure provides a high-speed regenerative comparator circuit, including: a signal input stage connected with an input terminal for differential signal input; a latch for caching and serving as a differential signal output terminal; a current source connected with the signal input stage for providing a power supply voltage; a fast path connected with the output terminal and used for increasing a voltage difference of the output terminal and turning on a positive feedback network of the latch; and a reset switch, including a first reset switch and a second reset switch. In the high-speed regenerative comparator circuit of the present disclosure, the transmission delay of the regenerative comparator circuit can be greatly reduced; and in a latch phase, a bias voltage is disconnected by means of timing control, and thus the power consumption of a comparator can be reduced. The present disclosure has simple circuit and high reliability.Type: GrantFiled: August 1, 2019Date of Patent: March 29, 2022Assignee: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATIONInventors: Xi Chen, Xiaofeng Shen, Xingfa Huang, Liang Li, Mingyuan Xu, Jian'an Wang, Dongbing Fu, Guangbing Chen
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Publication number: 20220091184Abstract: The present disclosure provides a differential clock cross point detection circuit and a detection method. The detection circuit includes: a first MOS transistor (M1), a second MOS transistor (M2) and a capacitor (C); a drain of the first MOS transistor (M1) is connected to a negative terminal (CLK?) of a differential clock, a gate of the first MOS transistor (M1) is connected to a positive terminal (CLK+) of the differential clock, and a source of the first MOS transistor (M1) is connected to a drain of the second MOS transistor (M2); a gate of the second MOS transistor (M2) is connected to the negative terminal (CLK?) of the differential clock, and a source of the second MOS transistor (M2) is connected to an output terminal through a node; one terminal of the capacitor (C) is connected to a node (A), and the other terminal of the capacitor (C) is grounded.Type: ApplicationFiled: January 7, 2020Publication date: March 24, 2022Applicants: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION, CHONGQING GIGACHIP TECHNOLOGY CO. LTD.Inventors: MINGYUAN XU, LIANG LI, JUN LIU, XIAOFENG SHEN, JIANAN WANG, DONGBING FU, GUANGBING CHEN, XINGFA HUANG, XI CHEN
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Publication number: 20220052673Abstract: The present disclosure provides a high-speed regenerative comparator circuit, including: a signal input stage connected with an input terminal for differential signal input; a latch for caching and serving as a differential signal output terminal; a current source connected with the signal input stage for providing a power supply voltage; a fast path connected with the output terminal and used for increasing a voltage difference of the output terminal and turning on a positive feedback network of the latch; and a reset switch, including a first reset switch and a second reset switch. In the high-speed regenerative comparator circuit of the present disclosure, the transmission delay of the regenerative comparator circuit can be greatly reduced; and in a latch phase, a bias voltage is disconnected by means of timing control, and thus the power consumption of a comparator can be reduced. The present disclosure has simple circuit and high reliability.Type: ApplicationFiled: August 1, 2019Publication date: February 17, 2022Applicant: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATIONInventors: Xi CHEN, Xiaofeng SHEN, Xingfa HUANG, Liang LI, Mingyuan XU, Jian'an WANG, Dongbing FU, Guangbing CHEN
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Patent number: 11251788Abstract: A duty cycle adjustment apparatus comprises a first edge extraction unit for extracting a rising edge of a first clock signal; a locking discrimination unit configured to output a control signal according to a comparison result between a discrimination voltage and a stabilized voltage, and select to connect the first clock signal or the clock output signal; an integration unit, configured to convert the feedback signal into the stabilized voltage, amplify the stabilized voltage to reach a reference voltage, and output a control voltage; a charge pump, configured to output a second clock signal according to the control voltage; a second edge extraction unit, configured to extract a falling edge of the second clock signal; and a phase discriminator, configured to compare a phase of the rising edge of the first clock signal with a phase of the falling edge of the second clock signal to generate the clock output signal.Type: GrantFiled: July 21, 2017Date of Patent: February 15, 2022Assignee: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATIONInventors: Xi Chen, Liang Li, Guangbing Chen, Yuxin Wang, Dongbing Fu, Xingfa Huang, Mingyuan Xu, Xiaofeng Shen
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Publication number: 20210280513Abstract: The present disclosure provides a one-time programmable capacitive fuse bit, including an upper plate, the upper plate includes a plurality of fuses arranged side by side and spaced by an internal from each other, middle portions of two adjacent fuses are connected to each other; a connecting portion connected to the fuse is disposed above two ends and the middle portion of each of the plurality of fuses; the fuse bit further includes a lower plate corresponding to the two ends and the middle portion of the fuse, the lower plate is disposed below the fuse; the lower plate corresponding to the middle portion of the fuse is opposite to the connecting portion corresponding to the middle portion of the fuse; a hollow portion is disposed between the lower plate corresponding to the middle portion of the fuse and the lower plate corresponding to both ends of the fuse.Type: ApplicationFiled: July 18, 2018Publication date: September 9, 2021Applicant: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATIONInventors: Mingyuan XU, Shuiqin YAO, Liang Li, Xiaofeng SHEN, Hongrui YANG, Jian'an WANG, Dongbing FU, Guangbing CHEN, Xingfa HUANG, Xi CHEN
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Publication number: 20210211122Abstract: A duty cycle adjustment apparatus comprises a first edge extraction unit for extracting a rising edge of a first clock signal; a locking discrimination unit configured to output a control signal according to a comparison result between a discrimination voltage and a stabilized voltage, and select to connect the first clock signal or the clock output signal; an integration unit, configured to convert the feedback signal into the stabilized voltage, amplify the stabilized voltage to reach a reference voltage, and output a control voltage; a charge pump, configured to output a second clock signal according to the control voltage; a second edge extraction unit, configured to extract a falling edge of the second clock signal; and a phase discriminator, configured to compare a phase of the rising edge of the first clock signal with a phase of the falling edge of the second clock signal to generate the clock output signal.Type: ApplicationFiled: July 21, 2017Publication date: July 8, 2021Applicant: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATIONInventors: Xi Chen, Liang Li, Guangbing Chen, Yuxin Wang, Dongbing Fu, Xingfa Huang, Mingyuan Xu, Xiaofeng Shen
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Publication number: 20210184689Abstract: The present disclosure provides a circuit for generating a multi-phase clock having random disturbance added thereto. The circuit for generating a clock includes a main clock module, a random signal generation module and a buffer matrix switch module. The main clock module generates N multi-phase clock signals; and the buffer matrix switch module randomly switches, under the control of a random control signal output by the random signal generation module, transmission paths of the input N multi-phase clock signals, and outputs N multi-phase clock signals with random disturbance. In the present disclosure, the clock phase error is whitened by adding random disturbance. Only with a small loss of signal-to-noise ratio, the influence of a multi-phase clock phase error on the performance of a high-precision TI ADC can be eliminated in real time, and the influence of the fluctuation of a clock phase error can be tracked and eliminated.Type: ApplicationFiled: December 13, 2018Publication date: June 17, 2021Applicant: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATIONInventors: Jie PU, Gangyi HU, Dongbing FU, Zhengping ZHANG, Liang LI, Ting LI, Daiguo XU, Mingyuan XU, Xiaofeng SHEN, Xianjie WAN, Youhua WANG
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Publication number: 20210135641Abstract: The present disclosure provides a clock driver circuit, including: an input stage, a double-ended to single-ended conversion stage and a driver output stage connected in sequence. The input stage includes two mutually loaded differential amplifiers and a common mode negative feedback loop. The differential amplifiers are connected to a differential clock signal for amplification to generate a common mode voltage. The common mode feedback circuit is connected to an output end of the differential amplifiers to stabilize the output amplitude of the common mode voltage. The double-ended to single-ended conversion stage converts a differential sine clock signal output by the double-ended common mode voltage into a single-ended square wave clock signal. The driver output stage includes a multi-stage cascaded push-pull phase inverter to improve the drive capability of the square wave clock signal.Type: ApplicationFiled: July 25, 2018Publication date: May 6, 2021Applicant: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATIONInventors: Xiaofeng SHEN, Xingfa HUANG, Liang LI, Xi CHEN, Mingyuan XU, Jian'an WANG, Dongbing FU, Guangbing CHEN
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Patent number: 10389787Abstract: Embodiments of the present invention relate to a method, an apparatus and a system for transmitting a media stream. The method is executed by an access terminal, includes: establishing a real-time collaboration channel between the access terminal and a network computer; sending through a first VDI channel to the network computer an operation instruction input by a user; receiving a real-time collaboration message that is sent through the real-time collaboration channel by the network computer; performing, through the network computer, media negotiation with a communication device, so as to determine a media attribute parameter that is used to transmit a media stream between the access terminal and the communication device; and transmitting, by the access terminal, a media stream mutually with the communication device according to the media attribute parameter determined through the media negotiation.Type: GrantFiled: November 25, 2014Date of Patent: August 20, 2019Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Mingyuan Xu, Qiang Yan