Abstract: An antifuse programming and detecting circuit has an antifuse which is capable of being programmed to an open state or to a short state. The circuit includes a latch circuit coupled with a power supply; a programming circuit for setting the antifuse state; and a reset circuit for resetting the output signal. The latch circuit provides and latches an output signal by detecting an antifuse state. Therefore, the state of the antifuse can be programmed, identified, and latched by the circuit design in the invention. The programming and detecting operations of the circuit provides programming, current limiting, detecting, and latching functions with simplified design and reduced number of devices.

Abstract: A pre-charge and isolation circuit for a folded bit line DRAM array to reduce noise coupling between adjacent bit lines of a DRAM array by connecting only one bit line within one sub-array to be connected to a sense amplifier, while the complementary bit line used for the reference voltage of the sense amplifier is selected from an adjacent sub-array, is disclosed. The isolation pre-charge circuit will be connected to a pair of bit lines within a DRAM array to pre-charge portions the pair of bit lines to a reference voltage level and to connect a selected DRAM cell to a latching sense amplifier.

Abstract: A voltage reference circuit that will remain constant and independent of changes in the operating temperature that is correlated to the bandgap voltage of silicon is described. The voltage reference circuit will be incorporated within an integrated circuit and will minimize currents into the substrate. The bandgap voltage reference circuit has a bandgap voltage referenced generator that will generate a first referencing voltage having a first temperature coefficient, and a compensating voltage generator that will generate a second referencing voltage having a second temperature coefficient. The second temperature coefficient is approximately equal and of opposite sign to the first temperature coefficient. A voltage summing circuit will sum the first referencing voltage and the second referencing voltage to create the temperature independent voltage.

Abstract: A data-line sense amplifier circuit for the sensing, amplifying and writing of digital data to and from a set of I/O lines from a bit line sense amplifying circuit is described. The data-line sense amplifier has a differential amplifier that is connected to positive and a negative primary data lines of the bit line sense amplifier. The change in the voltage in the positive and negative primary data lines is amplified and transferred to a positive and a negative output data lines. The data line sense amplifier has a writing means to transfer digital data that is present on the positive and negative output data lines to the positive and negative primary data lines. Multiple data line sense amplifiers may be cascaded between the bit line sense amplifying circuit and the input/output lines. A positive and negative timing control signal selectively activates and deactivates said differential amplifier for the low consumption of power.

Abstract: A double polysilicon dual gate LDMOSFET structure combined with a detecting circuit can be used to reduce the ON state resistance and without degradation of the breakdown voltage of the LDMOSFET. In the ON state, a drift region is driven into accumulation. In the OFF state, a gate is made to float and thereby avoid degradation of the breakdown voltage. A switch or transistor is modulated to either allow applied voltage to bias the gate for enabling the drift region to be driven into accumulation or to cause the gate to float to prevent the driving of the drift region by the voltage.

Abstract: A buffer circuit for connecting a CMOS logic circuit to receive TTL logic level signals assures that the upper and lower FET's of an otherwise conventional input inverter stage do not both turn on together in the situation in which an input signal has a level that is high enough to turn on the lower FET but not high enough to turn off the upper FET. A third and a fourth FET are connected to form a controlled power supply stage that controls the current supplied to the upper FET. The third FET has its gate connected to be controlled from the output of a second inverter stage (which is in phase with the input to the first stage). When the TTL input rises, the second inverter stage output turns off the third FET and thereby turns off the upper FET. The fourth FET is connected as a capacitor that is charged while the third FET is turned on and then supplies current to switch the output inverter stage when the upper FET is turned on.