Abstract: A method and apparatus for scalable video coding are disclosed, wherein the video data is configured into a Base Layer (BL) and an Enhancement Layer (EL) and wherein the EL has higher spatial resolution or better video quality than the BL. According to embodiments of the present invention, information from the base layer is exploited for coding the enhancement layer. The information coding for the enhancement layer includes CU structure, motion vector predictor (MVP) information, MVP/merge candidates, intra prediction mode, residual quadtree information, texture information, residual information, context adaptive entropy coding, Adaptive Lop Filter (ALF), Sample Adaptive Offset (SAO), and deblocking filter.

Abstract: A circuit board structure includes an inner circuit structure and a first build-up circuit structure. The inner circuit structure includes a core layer having an upper surface and a lower surface, a first patterned circuit layer disposed on the upper surface, a second patterned circuit layer disposed on the lower surface and a conductive through hole connecting the first and the second patterned circuit layers. The first build-up circuit structure at least has a cavity and an inner dielectric layer. The inner dielectric layer has an opening communicating the cavity and a pad of the first patterned circuit layer is located in the opening. A hole diameter of the opening is smaller than a hole diameter of cavity. An inner surface of the inner dielectric layer exposed by the cavity and a top surface of the pad are coplanar or have a height difference.

Abstract: A six-piece optical lens for capturing image and a six-piece optical module for capturing image are provided. In the order from an object side to an image side, the optical lens along the optical axis includes a first lens with refractive power; a second lens with refractive power; a third lens with refractive power; a fourth lens with refractive power; a fifth lens with refractive power; a sixth lens with refractive power; and at least one of the image-side surface and object-side surface of each of the six lens elements is aspheric. The optical lens can increase aperture value and improve the imagining quality for use in compact cameras.

Abstract: An optical image capturing system includes, along the optical axis in order from an object side to an image side, a first lens, a second lens, a third lens, a fourth lens, a fifth lens, a sixth lens, and a seventh lens. At least one lens among the first to the sixth lenses has positive refractive force. The seventh lens can have negative refractive force, wherein both surfaces thereof are aspheric, and at least one surface thereof has an inflection point. The lenses in the optical image capturing system which have refractive power include the first to the seventh lenses. The optical image capturing system can increase aperture value and improve the imagining quality for use in compact cameras.

Abstract: A method and apparatus for loop processing of reconstructed video in an encoder system are disclosed. The loop processing comprises an in-loop filter and one or more adaptive filters. The filter parameters for the adaptive filter are derived from the pre-in-loop video data so that the adaptive filter processing can be applied to the in-loop processed video data without the need of waiting for completion of the in-loop filter processing for a picture or an image unit. In another embodiment, two adaptive filters derive their respective adaptive filter parameters based on the same pre-in-loop video data. In yet another embodiment, a moving window is used for image-unit-based coding system incorporating in-loop filter and one or more adaptive filters. The in-loop filter and the adaptive filter are applied to a moving window of pre-in-loop video data comprising one or more sub-regions from corresponding one or more image units.

Abstract: A manufacturing method of an interposed substrate is provided. A photoresist layer is formed on a metal carrier. The photoresist layer has plural of openings exposing a portion of the metal carrier. Plural of metal passivation pads and plural of conductive pillars are formed in the openings. The metal passivation pads cover a portion of the metal carrier exposed by openings. The conductive pillars are respectively stacked on the metal passivation pads. The photoresist layer is removed to expose another portion of the metal carrier. An insulating material layer is formed on the metal cattier. The insulating material layer covers the another portion of the metal carrier and encapsulates the conductive pillars and the metal passivation pads. An upper surface of the insulating material layer and a top surface of each conductive pillar are coplanar. The metal carrier is removed to expose a lower surface of the insulating material layer.

Abstract: A protocol transparent retimer circuit monitors certain link layer control signals, detects far-end receiver parameters of the link partners, and detects attributes of the data signal on the link to determine the link status and operate the retimer in accordance with the determined link status. By combining and reducing host and device system states into a few retimer states, the retimer circuit is largely simplified and yet still serves its purpose. The retimer includes a controller that employs a state machine to interpret the monitored and detected signals to determine the link state and operate the retimer in an operating state corresponding to the determined link state. The approach enables the retimer to restore signal integrity and forward what ever it receives in both downstream and upstream directions of the link without frequency alteration.

Abstract: The present disclosure provides a semiconductor package device comprising a substrate, a semiconductor device, a first electronic component, an antenna pattern and a first package body. The substrate has a first area and a second area. The semiconductor device is disposed on the first area of the substrate. The first electronic component is disposed on the second area of the substrate. The antenna pattern is disposed on the second area of the substrate and electrically connected to the first electronic component. The first package body encapsulates the first area of the substrate and the semiconductor device and exposes the antenna pattern, the first electronic component and the second area of the substrate.

Abstract: A method for performing a method for performing a performing a face tracking function in an electric device is provided. The electric device has a touch panel, a camera, and a processor. The method includes the following steps. A touch signal is receiving by the touch panel. Under a video call, a face tracking mode is entered based on the touch signal by the processor. Face tracking is performed on a captured frame from the camera to obtain at least one region of interesting (ROI) of the captured frame by the processor, each of the ROI having an image of a face. A target frame is generated by combining the at least one ROI by the processor. The target frame is transmitted to another electric device by the processor, so that the target frame is shown on the another electric device as a video talk frame.

Abstract: A sound recording module including a sound-collecting space, a sound wave inlet, and a sound-receiving element is provided. The sound-collecting space at least has a reflecting zone. The reflecting area is adjacent to a first sound wave gathering zone and a second sound gathering zone, respectively. The first sound wave gathering zone appears in form of a hand web and defines a sound-receiving element fixing portion in the deepest position of the first sound gathering zone. The sound wave inlet is correspondingly formed on at least part of a periphery of the second sound gathering zone. The sound-receiving element is disposed at the sound-receiving element fixing portion of the first sound gathering zone. The sound-receiving element is configured to record a sound entering the sound-collecting space.

Abstract: Package structures and methods for forming the same are provided. The package structure includes an integrated circuit die and a first shielding feature over a base layer. The package structure also includes a package layer encapsulating the integrated circuit die and the first shielding feature. The package structure further includes a second shielding feature extending from the side surface of the base layer towards the first shielding feature to electrically connect to the first shielding feature. The side surface of the second shielding feature faces away from the side surface of the base layer and is substantially coplanar with the side surface of the package layer.

Abstract: A semiconductor structure includes a substrate including a first surface, a second surface opposite to the first surface and a recess extending from the first surface towards the second surface, a first die at least partially disposed within the recess and including a first die substrate and a first bonding member disposed over the first die substrate, a second die disposed over the first die and including a second die substrate and a second bonding member disposed a second die substrate and the second die substrate, a redistribution layer (RDL) disposed over the second die, and a conductive bump disposed over the RDL, wherein the first bonding member is disposed opposite to and is bonded with the second bonding member.

Abstract: The present invention provides a manufacture method of a TFT substrate structure and a TFT substrate structure. In the manufacture method of the TFT substrate structure, as manufacturing the gate, a plurality of metal sections distributed in spaces are formed at two sides of the gate, and the gate and the plurality of metal sections are employed to be a mask to implement ion implantation to the polysilicon layer. In the TFT substrate structure according to the present invention, the undoped areas are formed among the n-type heavy doping areas while forming the n-type heavy doping areas at the polysilicon layer.

Abstract: A semiconductor structure includes a semiconductor substrate and a conductive element formed in a portion of the semiconductor substrate. The semiconductor structure further includes a plurality of insulating elements formed in portions of the semiconductor substrate at a first region surrounding the conductive element and a semiconductor device formed over a portion of the semiconductor substrate at a second region adjacent to the first region. The first region is formed between the conductive element and the second region.

Abstract: Legacy bus operations, such as x86 I/O instructions having an address space separate from memory address space, are supported in a system in which I/O devices are coupled to a microcontroller connected via an SPI bus or other bit-serial bus. Each legacy bus operation is recognized and trapped by an interface controller, such as a south-bridge controller, which maps the trapped legacy bus operation into a corresponding bit-serial bus transaction, and transacts this corresponding bit-serial bus transaction on the bit-serial bus. Existing software infrastructure using x86 I/O instructions can remain intact, with I/O transactions bound for the SPI bus.

Abstract: A method of forming a semiconductor structure is provided. A substrate having a memory region is provided. A plurality of fin structures are provided and each fin structure stretching along a first direction. A plurality of gate structures are formed, and each gate structure stretches along a second direction. Next, a dielectric layer is formed on the gate structures. A first patterned mask layer is formed, wherein the first patterned mask layer has a plurality of first trenches stretching along the second direction. A second patterned mask layer on the first patterned mask layer, wherein the second patterned mask layer comprises a plurality of first patterns stretching along the first direction. Subsequently, the dielectric layer is patterned by using the first patterned mask layer and the second patterned mask layer as a mask to form a plurality of contact vias. The contact holes are filled with a conductive layer.

Abstract: A fin structure cutting process includes the following steps. Four fin structures are formed in a substrate, where the four fin structures including a first fin structure, a second fin structure, a third fin structure and a fourth fin structure are arranged sequentially and parallel to each other. A first fin structure cutting process is performed to remove top parts of the second fin structure and the third fin structure, thereby a first bump being formed from the second fin structure, and a second bump being formed from the third fin structure. A second fin structure cutting process is performed to remove the second bump and the fourth fin structure completely, but to preserve the first bump beside the first fin structure. Moreover, the present invention provides a fin structure formed by said process.

Abstract: A method for manufacturing fins includes following steps. A substrate including a plurality of fins formed thereon is provided. At least an ion implantation is performed to the fins. A thermal process is performed after the ion implantation. An insulating layer is formed on the substrate, and the fins are embedded in the insulating layer. Thereafter, a portion of the insulating layer is removed to form an isolation structure on the substrate, and the fins are exposed from a top surface of the isolation structure. The insulating layer is formed after the ion implantation and the thermal process. Or, the isolation structure is formed before the ion implantation, or between the ion implantation and the thermal process.

Abstract: A combined lens module including plural lens modules deposited within a housing is provided. These lens modules include plural lenses and multiple apertures. Each lens has a main lens element for visible light and an associate lens element for invisible light. An image capturing-and-sensing assembly may be performed by equipping with such a combined lens module and a sensor for visible light and invisible light, which could have high-resolution and apply to a thin portable device or any environment in use of infrared structured lighting or light scanner for the applications of human-machine interactive.

Abstract: The present disclosure relates to a method of bump metrology that relies upon advanced process control (APC) to provide substrate warpage parameters describing a warpage of a substrate to a bump metrology module to improve focus of the bump metrology module. In some embodiments, the method measures one or more substrate warpage parameters of a semiconductor substrate. An initial focal height of a lens of a bump metrology module is calculated based upon the measured substrate warpage parameters. The lens of the bump metrology module is then placed at the initial focal height, and height and critical dimensions of a plurality of bumps on the semiconductor substrate are subsequently measured using the lens. By providing the substrate warpage parameters to the bump metrology module, the bump metrology module can use real-time process control to account for wafer warpage, thereby improving throughput and yield.