Abstract: The present invention provides a preparation method of pharmaceutical composition for treating chronic stroke, involving injection via brain into the cranium of a patient having chronic stroke for six months or more; the pharmaceutical composition is a suspension at least comprising adipose-derived stem cells treated by cell expansion, an active synergistic component and a growth factor, wherein the expression level of CD34 and CD45 of the adipose-derived stem cells treated by cell expansion is 10% or less, and the expression level of CD90 and CD105 is 90% or more; the active synergistic component is an extracellular vesicle; the growth factor is at least one selected from the group consisting of HGF, G-CSF, Fractalkine, IP-10, EGF, IL-1?, IL-1?, IL-4, IL-5, IL-13, IFN?, TGF? and sCD40L. The present invention overcomes the limitations of previous cell therapy and provides a cell-based preparation that is clinically safe and therapeutically effective for chronic cerebral stroke.

Abstract: A display device includes a first pixel and a second pixel. The first pixel includes first light-emitting diodes. Each first light-emitting diode includes a first bottom semiconductor layer and a first top semiconductor layer stacked along a vertical direction. The second pixel includes second light-emitting diodes. Each second light-emitting diode includes a second bottom semiconductor layer and a second top semiconductor layer stacked along the vertical direction. In one of the first light-emitting diodes of the first pixel, a first mesa region is located in a first direction of a first overlap region, and in another of the first light-emitting diodes of the first pixel, the first mesa region is located in a second direction opposite to the first direction of the first overlap region. In each second light-emitting diode of the second pixel, a second mesa region is located in the second direction of a second overlap region.

Abstract: Provided is a reticle pod with a detachable supporting mechanism, which is suitable for a dual pod, including an outer pod and an inner pod received therein, the inner pod including: a base, and at least a supporting mechanism, mounted on the base. The supporting mechanism includes: a supporting assembly, connected to a mounting interface of the base, the supporting assembly includes a seat, at least one limiting post, and a mounting hole, the at least one limiting post connects to the seat, the mounting hole penetrates the base and not a circular hole; and a supporting element, having a matching structure, so that the supporting element detachably received in the mounting hole.

Abstract: A device includes a fin protruding from a semiconductor substrate; a gate stack over and along a sidewall of the fin; a gate spacer along a sidewall of the gate stack and along the sidewall of the fin; an epitaxial source/drain region in the fin and adjacent the gate spacer; and a corner spacer between the gate stack and the gate spacer, wherein the corner spacer extends along the sidewall of the fin, wherein a first region between the gate stack and the sidewall of the fin is free of the corner spacer, wherein a second region between the gate stack and the gate spacer is free of the corner spacer.

Abstract: Disclosed herein is a drug complex having a synthetic peptide, which has an amino acid sequence of SEQ ID: NO.1; a metal chelator coupled to the synthetic peptide; and a peptide chain disposed between the synthetic peptide and the metal chelator, wherein the peptide chain is composed of plural glutamate molecules.

Abstract: A cyclic process including an etching process, a passivation process, and a pumping out process is provided to prevent over etching of the sacrificial gate electrode, particularly when near a high-k dielectric feature. The cyclic process solves the problems of failed gate electrode layer at an end of channel region and enlarges filling windows for replacement gate structures, thus improving channel control. Compared to state-of-art solutions, embodiments of the present disclosure also enlarge volume of source/drain regions, thus improving device performance.

Abstract: An imaging lens assembly module includes an imaging lens assembly and a variable aperture module. The imaging lens assembly has an optical axis. The variable aperture module includes a light blocking sheet set, a fixed element, a movable element, and an annular light blocking portion. The light blocking sheet set includes at least two light blocking sheets, wherein the at least two light blocking sheets are mutually stacked along a circumferential direction surrounding the optical axis to form a variable aperture opening. The fixed element has a sidewall structure. The annular light blocking portion surrounds the optical axis to form a fixed aperture opening.

Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another, a gate structure that comprises a lower portion and an upper portion, a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface, and an etch stop layer extends between the portion of the bottom surface of the gate spacer and the top surface of the topmost semiconductor layer.

Abstract: A method of fabricating a semiconductor structure includes forming a recess in an active channel structure by removing a portion thereof, filling the recess with a dielectric material, forming a cladding layer adjacent the active channel structure but not adjacent the dielectric material, and forming a gate structure comprising a first gate structure and a second gate structure around the active channel structure. A width of the dielectric material in the recess is greater than a width of the first gate structure and a width of the second gate structure.

Abstract: A display panel, including a circuit substrate, a light emitting diode, and a reflective layer, is provided. The light emitting diode includes a light emitting layer and first and second semiconductor layers. The light emitting layer is located between the first and second semiconductor layers. The second semiconductor layer is located between the first semiconductor layer and the circuit substrate. The reflective layer is in contact with a part of a side surface of the light emitting diode. A part of the reflective layer is located between the light emitting diode and the circuit substrate. Taking a direction perpendicular to a top surface of the circuit substrate as a height direction, a horizontal height of a top surface of the reflective layer is located between a horizontal height of a top surface of the light emitting layer and a horizontal height of a top surface of the light emitting diode.

Abstract: A biocompatible magnetic material containing an iron oxide nanoparticle and one or more biocompatible polymers, each having formula (I) below, covalently bonded to the iron oxide nanoparticle: in which each of variables R, L, x, and y is defined herein, the biocompatible magnetic material contains 4-15% Fe(II) ions relative to the total iron ions. Also disclosed in a method of preparing the biocompatible magnetic material.

Abstract: A method of forming a semiconductor structure, includes forming a fin structure over a substrate in a Z-direction; forming a dummy gate structure extending in a Y-direction and over the fin structure; and forming gate spacers on sidewalls of the dummy gate structure. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method further includes removing a portion of the dummy gate structure to form a first trench that exposes upper portions of the gate spacers; forming an insulating material in the first trench; partially removing the insulating material to form insulating layers on sidewalls of the upper portions of the gate spacers; removing a remaining portion of the dummy gate structure to expose lower portions of the gate spacers; and partially etching the lower portions of the gate spacers.

Abstract: The present invention relates to a cell differentiation medium composition, a high secretion insulin-producing cells and a preparation method thereof. The high secretion insulin-producing cells obtained by using the cell differentiation medium composition to induce stem cell differentiated under specific conditions can secrete a large amount of insulin in a short time, and when the high-secreting insulin-producing cells are transplanted into the human body, they are not easy to be swallowed by macrophages, which can improve the survival rate of the insulin-producing cells and prolong the time of insulin secretion thereby.

Abstract: An image sensor structure and methods of forming the same are provided. An image sensor structure according to the present disclosure includes a semiconductor substrate including a photodiode, a transfer gate transistor disposed over the semiconductor substrate and having a first channel area, a first dielectric layer disposed over the semiconductor substrate, a semiconductor layer disposed over the first dielectric layer, a source follower transistor disposed over the semiconductor layer and having a second channel area, a row select transistor disposed over the semiconductor layer and having a third channel area, and a reset transistor disposed over the semiconductor layer and having a fourth channel area. The second channel area is greater than the first channel area, the third channel area or the fourth channel area.

Abstract: An electronic device includes a casing, an antenna, and a connector. The casing includes a metal layer and a first slot and a second slot located on the metal layer. The metal layer includes a metal connecting segment, a first region, and a second region. The metal connecting segment is located between the first slot and the second slot, and the first region and the second region are separated by the first slot, the second slot, and the metal connecting segment. The antenna is connected to the first region, and the antenna is adapted to resonate at a frequency band. The connector is connected to the second region.

Abstract: A method of forming a semiconductor device includes: forming a via in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; forming an opening in the second dielectric layer, where the opening exposes an upper surface of the via; selectively forming a capping layer over the upper surface of the via, where the capping layer has a curved upper surface that extends above a first upper surface of the first dielectric layer distal from the substrate; after forming the capping layer, forming a barrier layer in the opening over the capping layer and along sidewalls of the second dielectric layer exposed by the opening; and filling the opening by forming an electrically conductive material over the barrier layer.

Abstract: A semiconductor device includes a first fin and a second fin in a first direction and aligned in the first direction over a substrate, an isolation insulating layer disposed around lower portions of the first and second fins, a first gate electrode extending in a second direction crossing the first direction and a spacer dummy gate layer, and a source/drain epitaxial layer in a source/drain space in the first fin. The source/drain epitaxial layer is adjacent to the first gate electrode and the spacer dummy gate layer with gate sidewall spacers disposed therebetween, and the spacer dummy gate layer includes one selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride.

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate over the fin; reducing a thickness of a lower portion of the dummy gate proximate to the isolation regions, where after reducing the thickness, a distance between opposing sidewalls of the lower portion of the dummy gate decreases as the dummy gate extends toward the isolation regions; after reducing the thickness, forming a gate fill material along at least the opposing sidewalls of the lower portion of the dummy gate; forming gate spacers along sidewalls of the dummy gate and along sidewalls of the gate fill material; and replacing the dummy gate with a metal gate.

Abstract: A heating device includes a resonant circuit, a detection unit and a control unit. The resonant circuit includes an inverter circuit and a resonant tank. The inverter circuit provides a resonant tank current and a resonant tank voltage. The resonant tank includes a heating coil, a resonant tank capacitor, a resonant tank equivalent inductor and a resonant tank equivalent resistor. The detection unit calculates an inductance of the resonant tank equivalent inductor according to a capacitance of the resonant tank capacitor, a resonant period and a first expression. The detection unit calculates a resistance of the resonant tank equivalent resistor according to the inductance of the resonant tank equivalent inductor, a time change value, a reference voltage value, a negative peak voltage value and a second expression.

Abstract: A method for searching a path by using a 3D reconstructed map includes: receiving 3D point-cloud map information and 3D material map information; clustering the 3D point-cloud map information with a clustering algorithm to obtain clustering information, and identifying material attributes of objects in the 3D point-cloud map information with a material neural network model to obtain material attribute information; fusing the those map information based on their coordinate information, thereby outputting fused map information; identifying obstacle areas and non-obstacle areas in the fused map information based on an obstacle neural network model, the clustering information, and the material attribute information; and generating 3D path information according to the non-obstacle areas. Since the 3D path information is generated based on those map information, the obstacle areas and flight spaces are effectively determined to generate an accurate flight path.