Abstract: A semiconductor chip includes a first intellectual property block. There are a second intellectual property block and a third intellectual property block around the first intellectual property block. There is a multiple metal layer stack over the first intellectual property block, the second intellectual property block, and the third intellectual property block. An interconnect structure is situated in the upper portion of the multiple metal layer stack. The interconnect structure is configured for connecting the first intellectual property block and the second intellectual property block. In addition, at least a part of the interconnect structure extends across and over the third intellectual property block.

Abstract: A CMOS image sensor includes PDAF pixels distributed in an array of image pixels in plan view. Each PDAF pixel includes m×m binned photodiodes, a PDAF color filter overlying the binned photodiodes and laterally surrounded by a first isolation structure, and a PDAF micro-lens overlying the PDAF color filter. A first horizontal distance between a center of the PDAF color filter and a center of the binned photodiodes varies depending on a location of the PDAF pixel in plan view in the CMOS image sensor. Additionally, the first isolation structure includes a first low-n dielectric grid, a second low-n dielectric grid underlying the first low-n dielectric grid, and a metal grid enclosed by the second low-n dielectric grid. The second low-n dielectric grid includes a filler dielectric material different from a second low-n dielectric grid material. Thus, quantum efficiency and uniformity of the CMOS image sensor are improved.

Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.

Abstract: The present invention discloses a portable electronic apparatus, which includes a cover casing, a base casing, a first input module and a second input module. The base casing is pivoted to the cover casing, and the base casing includes a containing portion and at least one first connecting portion. The containing portion is located on the base casing, and the first connecting portion is disposed on the containing portion. The first input module and the second input module are disposed on the containing portion interchangeably, the first input module has a second connecting portion, and the second input module has a third connecting portion. When the first input module is disposed on the containing portion, the second connecting portion electrically connects to the first connecting portion. When the second input module is disposed on the containing portion, the third connecting portion electrically connects to the first connecting portion.

Abstract: A clamshell electronic device is disclosed. The clamshell electronic device includes a first cover, a second cover and a pivoting element. The second cover system is provided to dispose a first input module or a second input module, wherein the first input module and the second input module have different heights. The pivoting element connects the first cover and the second cover to allow the first cover and the second cover to rotate with each other. When the second cover is disposed with the first input module or the second input module, the pivoting element can be adjusted to a first use state and a second use state.

Abstract: The present invention discloses a portable electronic apparatus, which includes a cover casing, a base casing, a first keyboard and a second keyboard. The base casing is pivoted to the cover casing. The base casing includes a keyboard containing portion and a first connecting portion, and the first connecting portion is disposed on the keyboard containing portion. The first keyboard and the second keyboard are disposed in the keyboard containing portion interchangeably, the first keyboard has a second connecting portion, and the second keyboard has a third connecting portion. When the first keyboard is disposed in the keyboard containing portion, the second connecting portion is electrically connected to the first connecting portion. When the second keyboard is disposed in the keyboard containing portion, the third connecting portion is electrically connected to the first connecting portion.

Abstract: A clamshell electronic device is disclosed. The clamshell electronic device includes a first cover, a second cover and a pivoting element. The second cover system is provided to dispose a first input module or a second input module, wherein the first input module and the second input module have different heights. The pivoting element connects the first cover and the second cover to allow the first cover and the second cover to rotate with each other. When the second cover is disposed with the first input module or the second input module, the pivoting element can be adjusted to a first use state and a second use state.

Abstract: The present invention discloses a portable electronic apparatus, which includes a cover casing, a base casing, a first input module and a second input module. The base casing is pivoted to the cover casing, and the base casing includes a containing portion and at least one first connecting portion. The containing portion is located on the base casing, and the first connecting portion is disposed on the containing portion. The first input module and the second input module are disposed on the containing portion interchangeably, the first input module has a second connecting portion, and the second input module has a third connecting portion. When the first input module is disposed on the containing portion, the second connecting portion electrically connects to the first connecting portion. When the second input module is disposed on the containing portion, the third connecting portion electrically connects to the first connecting portion.

Abstract: An apparatus for stabilizing a ladder. In one embodiment, the apparatus comprises a frame releasably attachable to the ladder, and one or more stabilizer arms extending from the frame. The apparatus may include one or more clamps rotatably disposed on the frame for securing the apparatus on the ladder, and the one or more clamps may be disposed in a fixed rotational relationship with the one or more stabilizer arms. The frame may comprise a first and second brace members disposed in mating engagement, and the first and second brace members may be adjustably securable to each other by releasable fasteners.

Abstract: A chemical mechanical polishing (CMP) apparatus with temperature control. The apparatus controls circular zone temperature of the wafer. The CMP apparatus comprises a platen; a carrier holding a wafer against the platen; a guide ring disposed at the rim of the carrier to mount the wafer on the carrier; and a heater disposed in the guide ring, in the carrier, or used to heat the slurry. The temperature of the heater is set between 20° C. and 60° C. Thus, the polishing rate at the edge is improved, and the polishing difference between the edge and the center of the wafer is reduced.

Abstract: A method for avoiding defects produced in The CMP process has the following steps: sequentially depositing a first dielectric layer and a second dielectric layer on a semiconductor substrate, wherein the wet-etching rate of the first dielectric layer is greater than the wet-etching rate of the second dielectric layer; forming a plurality of first holes on a plurality of the predetermined contact window areas respectively; wet etching the first dielectric layer in each of the first holes to form a plurality of second holes on the plurality of the predetermined contact window areas respectively; forming a conductive layer to fill each of the second holes; and performing the CMP process to level off the conductive layer and the second dielectric layer.

Abstract: A chemical-mechanical polishing platform that comprises a polishing table, a wafer carrier, a polishing pad, a slurry supplier, a conditioner, and a means for cleaning the polishing pad. With respect to in-situ or ex-situ chemical-mechanical polishing, the wafer carrier, conditioner, and means for cleaning the polishing pad are adequately disposed above the polishing pad. The chemical-mechanical polishing is performed by rotation of the polishing pad; the region of the polishing pad that has polished the wafer then passes sequentially through the conditioner, the means for cleaning that removes diamond particles that may drop on the polishing pad, and through the slurry supplier that provides adequate slurry such that the polishing process can be repeated without scraping damage of the wafer. The means for cleaning of the present invention can have any shapes adapted to remove diamond particles on the polishing pad, such as circular or cylindrical brush sweeper.

Abstract: A method for avoiding defects produced in The CMP process has the following steps: sequentially depositing a first dielectric layer and a second dielectric layer on a semiconductor substrate, wherein the wet-etching rate of the first dielectric layer is greater than the wet-etching rate of the second dielectric layer; forming a plurality of first holes on a plurality of the predetermined contact window areas respectively; wet etching the first dielectric layer in each of the first holes to form a plurality of second holes on the plurality of the predetermined contact window areas respectively; forming a conductive layer to fill each of the second holes; and performing the CMP process to level off the conductive layer and the second dielectric layer.

Abstract: A chemical mechanical polishing (CMP) apparatus with temperature control. The apparatus controls circular zone temperature of the wafer. The CMP apparatus comprises a platen; a carrier holding a wafer against the platen; a guide ring disposed at the rim of the carrier to mount the wafer on the carrier; and a heater disposed in the guide ring, in the carrier, or used to heat the slurry. The temperature of the heater is set between 20° C. and 60° C. Thus, the polishing rate at the edge is improved, and the polishing difference between the edge and the center of the wafer is reduced.

Abstract: A semiconductor process for manufacturing a wafer. First, a previously predicted process rate and a previously measured process rate are provided by a process tool. Next, a presently predicted process rate is obtained by a first linear equation having a first variable weighting factor using the previously predicted process rate and the previously measured process rate as variables. Next, a process time is obtained according to the presently predicted process rate and a predetermined process target to input to the process tool. Finally, the wafer is manufactured according to the process time by the process tool.

Abstract: A method for avoiding defects produced in The CMP process has the following steps: sequentially depositing a first dielectric layer and a second dielectric layer on a semiconductor substrate, wherein the wet-etching rate of the first dielectric layer is greater than the wet-etching rate of the second dielectric layer; forming a plurality of first holes on a plurality of the predetermined contact window areas respectively; wet etching the first dielectric layer in each of the first holes to form a plurality of second holes on the plurality of the predetermined contact window areas respectively; forming a conductive layer to fill each of the second holes; and performing the CMP process to level off the conductive layer and the second dielectric layer.

Abstract: A new method is provided for determining the optimum film thickness of a film that is to be deposited over a semiconductor surface. The invention observes the electrical current and the therefrom resulting torque that is supplied to a rotating part of a polishing apparatus, from this the CMP end-point can be determined for a reference film that has been deposited. This technique is known as the “CMP end-point detection” technique. The invention addresses observing CMP end-point curves for films of various thicknesses and compares these CMP end-point curves of one film thickness with each other and calculates a deviation for multiple layers (deposited on different wafers) of that film thickness. The process is repeated for different film thickness. The film thickness that has a deviation of the CMP end-point curve that closest resembles an optimum deviation is the film thickness that is selected as having the optimum thickness for the deposition of that film.

Abstract: A device for chemical-mechanical polishing. The device can be applied to a chemical polishing table spinning in a fixed direction and a polishing pad above of it. A chemical-mechanical polishing device according to the present invention is at least comprised of a main body of conditioner with a plurality of mounting pads, wherein each mounting pad is mounted with the diamond granules and located on the lower surface of conditioner, distributed on the rim of main body of each mounting pad. It can contact with polishing pads when cleaning the polishing pads and a number of cavities are across the upper and lower surfaces of each main body of conditioner and distributed between each mounting pads as well. When using the conditioners to clean out the polishing pads, the de-ionized water will flow through the cavities to wash off the acid or basic slurry to eliminate the destruction made by the solders around the diamond granules to extend the durability of the conditioner.

Abstract: A method of monitoring the state of chemical-mechanical polishing that can be applied to the polishing of a metallic layer over a substrate. The method includes performing a series of scanning operations while a wafer is being polished to generate multiple reflectance line spectra in each polishing period. The degree of dispersion of the reflectance spectra is then utilized as a polishing index. In this invention, the standard deviation of the reflectance spectra in each period is used as a monitoring index, and the peak value of the standard deviation is used to determine the polishing end point. Surface uniformity is monitored by using the time interval between two time nodes at half the peak standard deviation values. When the distance of separation between the two time nodes is large, it means that the polished surface is not sufficiently flat.

Abstract: A brush comprises a sleeve, a cap member, a brushing member, and at least one elastic member. The sleeve has a first end and a second end. The brushing member is movably received in the sleeve at the first end, while the cap member is firmly coupled to the sleeve at the second end. The elastic member is disposed between the cap member and the brushing member so that a portion of the brushing member protrudes from the first end of the sleeve.