Abstract: A frequency divider circuit is described. The frequency divider circuit includes a first cross-coupling. The first cross-coupling includes a first cross-coupled transistor with a first gate. The first gate is separately biased. The first cross-coupling also includes a second cross-coupled transistor with a second gate. The second gate is separately biased. The first gate is coupled to the second cross-coupled transistor and the second gate is coupled to the first cross-coupled transistor.

Abstract: Exemplary techniques for DC offset calibration for complex filters are disclosed. A complex filter is provided having a first calibration path circuit and a second calibration path circuit, each including a first and a second set of switches, respectively. The first set of switches is enabled during calibration mode and the second set of switches is enabled during normal operation mode such that the network characteristics of each calibration path circuit are substantially the same during both modes of operation. In one embodiment, the complex filter is a low pass filter.

Abstract: A frequency divider circuit is described. The frequency divider circuit includes a first cross-coupling. The first cross-coupling includes a first cross-coupled transistor with a first gate. The first gate is separately biased. The first cross-coupling also includes a second cross-coupled transistor with a second gate. The second gate is separately biased. The first gate is coupled to the second cross-coupled transistor and the second gate is coupled to the first cross-coupled transistor.

Abstract: Various embodiments of the present invention provide systems and circuits that provide for out of band detection. As one example, an out of band detection circuit is disclosed that includes an input signal, a clock generation circuit, and a sampling circuit. The clock generation circuit receives the input signal and derives therefrom a sampling clock, and the sampling circuit is operable to sample the input signal at a time indicated by the sampling clock.

Abstract: Exemplary techniques for DC offset calibration for complex filters are disclosed. A complex filter is provided having a first calibration path circuit and a second calibration path circuit, each including a first and a second set of switches, respectively. The first set of switches is enabled during calibration mode and the second set of switches is enabled during normal operation mode such that the network characteristics of each calibration path circuit are substantially the same during both modes of operation. In one embodiment, the complex filter is a low pass filter.

Abstract: Various embodiments of the present invention provide systems and circuits that provide for out of band detection. As one example, an out of band detection circuit is disclosed that includes an input signal, a clock generation circuit, and a sampling circuit. The clock generation circuit receives the input signal and derives therefrom a sampling clock, and the sampling circuit is operable to sample the input signal at a time indicated by the sampling clock.

Abstract: Various embodiments of the present invention provide systems and circuits that provide for conversion of analog signals to digital signals. For example, various embodiments of the present invention provide pipelined analog to digital converters. Such converters include a sub-converter and a residue amplifier. The sub-converter receives an analog input, and provides a digital representation of the analog input including a number of bits. A gain of the residue amplifier is controlled by selectably setting a group of switches. Each of the number of bits output from the sub-converter electrically controls a respective one of the switches.

Abstract: Various embodiments of the present invention provide systems and circuits that provide for conversion of analog signals to digital signals. For example, various embodiments of the present invention provide methods for performing analog to digital conversions that include providing an analog to digital converter with a residue amplifier that is associated with a first capacitance set that includes a first feedback capacitor and first set of input capacitors, and a second capacitance set that includes a second feedback capacitor and second set of input capacitors. The methods further include performing a first sample of an analog input voltage by charging the first set of input capacitors from the analog voltage input during a first period; amplifying the first sample during a second period; performing a second sample of the analog input voltage by charging the second set of input capacitors from the analog voltage input during a third period; and amplifying the second sample during a fourth period.

Abstract: Various embodiments of the present invention provide systems and circuits that provide for conversion of analog signals to digital signals. For example, various embodiments of the present invention provide methods for performing analog to digital conversions that include providing an analog to digital converter with a residue amplifier that is associated with a first capacitance set that includes a first feedback capacitor and first set of input capacitors, and a second capacitance set that includes a second feedback capacitor and second set of input capacitors. The methods further include performing a first sample of an analog input voltage by charging the first set of input capacitors from the analog voltage input during a first period; amplifying the first sample during a second period; performing a second sample of the analog input voltage by charging the second set of input capacitors from the analog voltage input during a third period; and amplifying the second sample during a fourth period.

Abstract: Various embodiments of the present invention provide systems and circuits that provide for conversion of analog signals to digital signals. For example, various embodiments of the present invention provide pipelined analog to digital converters. Such converters include a sub-converter and a residue amplifier. The sub-converter receives an analog input, and provides a digital representation of the analog input including a number of bits. A gain of the residue amplifier is controlled by selectably setting a group of switches. Each of the number of bits output from the sub-converter electrically controls a respective one of the switches.

Abstract: Certain embodiments of the present invention relate to techniques for tuning or measuring operational features of amplifiers, such as the transconductance of operational transconductance amplifiers (OTAs) and the gain of variable gain amplifiers (VGAs). Each technique employs (at least) two phases that involve the application of different input voltages. The results of the multiple phases are then combined to generate a final result that negates or reduces the effects of real-world properties such as finite output impedances and offset voltages.

Abstract: A circuit is described which uses a thick gate oxide device in the input stage and a thin gate oxide device in a second stage that is connected to the input stage. The input stage thick gate oxide device provides a low input gate leakage current. The thin gate oxide device in the second stage has high performance characteristics due to the use of the thin gate oxide device. The circuit thereby has high performance characteristics and low input gate leakage current. In various applications, the circuit may be, for example, an amplifier, a differential amplifier, a variable gain differential amplifier, or an operational amplifier in a sample and hold circuit. A guideline is provided where the thick gate oxide layer is about 1.5× the thickness of the thin gate oxide layer. Also, a design to control the circuit's common mode voltage using common mode voltage feedback is described.

Abstract: Certain embodiments of the present invention relate to techniques for tuning or measuring operational features of amplifiers, such as the transconductance of operational transconductance amplifiers (OTAs) and the gain of variable gain amplifiers (VGAs). Each technique employs (at least) two phases that involve the application of different input voltages. The results of the multiple phases are then combined to generate a final result that negates or reduces the effects of real-world properties such as finite output impedances and offset voltages.

Abstract: Various systems and methods for converting a signal from the analog domain to the digital domain are disclosed herein. As one example, an analog-to-digital converter is disclosed that includes two pipelined analog-to-digital converter stages. The first analog-to-digital converter stage provides an encoded word output and the second analog-to-digital converter stage provides an unencoded word output. A summation device is provided to aggregate the encoded word output with the unencoded word output.

Abstract: A circuit is described which uses a thick gate oxide device in the input stage and a thin gate oxide device in a second stage that is connected to the input stage. The input stage thick gate oxide device provides a low input gate leakage current. The thin gate oxide device in the second stage has high performance characteristics due to the use of the thin gate oxide device. The circuit thereby has high performance characteristics and low input gate leakage current. In various applications, the circuit may be, for example, an amplifier, a differential amplifier, a variable gain differential amplifier, or an operational amplifier in a sample and hold circuit. A guideline is provided where the thick gate oxide layer is about 1.5× the thickness of the thin gate oxide layer. Also, a design to control the circuit's common mode voltage using common mode voltage feedback is described.

Abstract: A low power LVDS driver includes a switchable current module, a source termination circuit, a transistor section, and a load current source. The switchable current module is operably coupled to produce a first current when a differential input signal is in a first state and to produce a second current when the differential input signal is in a second state. The source termination circuit is operably coupled in parallel with a load. The transistor section is operably coupled to receive the first and second currents from the switchable current module via at least one of the source termination circuit and the load, wherein the transistor section produces an LVDS output signal based on the first and second currents, the differential input signal, and the source termination circuit. The load current source is operably coupled to sink the first and second currents from the transistor section.