Abstract: A cloud-based network security system (NSS) is described. The NSS uses a sandbox to safely detonate and extract information about a document and uses machine learning algorithms to analyze the information to predict whether the document contains malicious software. Specifically, during the detonation, static and dynamic information about the document is captured in the sandbox as well as character strings from images in the document. The dynamic information (and sometimes the static information) is input to an AI or machine learning model trained to provide an output indicating a prediction of whether the document contains malware. The character strings are compared with a batch of phishing keywords to generate a heuristic score. A validation engine combines the output from the AI or machine learning model and the heuristic score to classify the document as malicious or clean. Security policies can then be applied based on the classification.

Abstract: A method includes extracting electrons from a remote electron source to negatively charge upper surfaces of a patterned layer with the electrons, and extracting positive ions from a remote ion source to selectively deposit a material on the upper surfaces by attracting the positive ions to the electrons of the upper surfaces. The upper surfaces may be negatively charged by concurrently applying a positive bias at the patterned layer and applying source power with a lower power level to generate plasma. The material may be selectively deposited by concurrently applying a negative bias at the patterned layer and applying source power with a higher power level to plasma. An extraction grid may separate the patterned layer from the plasma. The extraction grid may be electrically floating or coupled to a ground potential during either of the electron extraction step or the ion extraction step.

Abstract: A method includes forming a gate structure over a silicon on insulator (SOI) substrate. The SOI substrate comprising: a base semiconductor layer; an insulator layer over the base semiconductor layer; and a top semiconductor layer over the insulator layer. The method further includes depositing a gate spacer layer over a top surface and along a sidewall of the gate structure; etching the gate spacer layer to define a gate spacer on the sidewall of the gate structure; after etching the gate spacer layer, etching a recess into the top semiconductor layer using a first etch process; and after the first etch process, extending the recess further into the top semiconductor layer using a second etch process. The first etch process is different from the second etch process. The method further includes forming a source/drain region in the recess after the second etch process.

Abstract: The present invention provides an integrated circuit layout including a first bank and a second bank. The first bank includes a plurality of I/O circuits and at least one first ESD clamp device. The second bank includes at least one second ESD clamp device, wherein the at least one second ESD clamp device is different in type from the at least one first ESD clamp device.

Abstract: An electronic system and an operating method for the electronic system are provided. The electronic system includes a programmable circuit, a memory circuit, a controller, and a switching circuit. The controller provides a first control signal. The switching circuit has a control terminal, a first terminal, a second terminal, and a third terminal. The first terminal is coupled to the programmable circuit. The second terminal is coupled to the memory circuit. The control terminal and the third terminal are coupled to the controller. The switching circuit receives the first control signal through the control terminal to connect the third terminal to the second terminal, so that update data is stored into the memory circuit.

Abstract: A method includes forming a transistor comprising a source/drain region and a gate electrode, forming a source/drain contact plug over and electrically connecting to the source/drain region, forming a first inter-layer dielectric over the source/drain contact plug, forming an etch stop layer over the first inter-layer dielectric, etching the etch stop layer to form a first via opening, forming a second inter-layer dielectric over the first inter-layer dielectric, performing an etching process, so that the second inter-layer dielectric is etched to form a trench, and the first via opening in the etch stop layer is extended into the first inter-layer dielectric to reveal the source/drain contact plug, and filling the trench and the first via opening in common processes to form a metal line and a via, respectively.

Abstract: The present disclosure provides a method and a non-transitory computer readable media for inter-metal dielectric reliability check. The method comprises: receiving an electronic layout, the electronic layout including a first plurality of electrical components in a first layer; determining an internal voltage difference within each electrical component in the first layer based on parasitic effect; generating a simulation voltage value for each electrical component in the first layer based on the internal voltage differences; and tagging a pair of electrical components in the first layer when a first voltage difference between the pair of electrical components exceeds a first voltage threshold. The first voltage difference is determined based on the simulation voltage value of each electrical component.

Abstract: A method includes forming a structure having a dummy gate stack over a fin protruding from a substrate. The fin includes an ML of alternating semiconductor layers and sacrificial layers. The method further includes forming a recess in an S/D region of the ML, forming a recess of the ML, and forming inner spacers on sidewalls of the sacrificial layers. Each inner spacer includes a first layer embedded in the sacrificial layer and a second layer over the first layer. The method further includes forming an S/D feature in the recess, such that the second layer of the inner spacers is embedded in the S/D feature. The method further includes removing the dummy gate stack to form a gate trench, removing the sacrificial layers from the ML, thereby forming openings interleaved between the semiconductor layers, and subsequently forming a high-k metal gate stack in the gate trench and the openings.

Abstract: A projection lens module includes a lens assembly, a reflector arranged beside the lens assembly, a housing assembly covering the reflector, and a buffer. The reflector includes a reflecting surface and a back surface opposite to each other; the reflecting surface faces the lens assembly to reflect a light beam passing through the lens assembly. The housing assembly includes a flow channel frame, an inner surface. The flow channel frame is arranged on the inner surface and protrudes toward the back surface. The buffer is sandwiched between the flow channel frame and the back surface. A flow channel is formed between the flow channel frame and the back surface and communicates with the air inlet and the air outlet.

Abstract: An electronic device is provided. The electronic device includes a plurality of processing units constituting a processing array having a first area, a surface supporting the processing array, and an optical channel. The surface has a second area, and the first area is greater than 80 percent of the second area. The optical channel is configured to transmit a first signal between at least two of the plurality of processing units in a first direction that is nonparallel with a normal direction of the surface.

Abstract: A method of forming a fin field effect transistor (finFET) on a substrate includes forming a fin structure on the substrate and forming a shallow trench isolation (STI) region on the substrate. First and second fin portions of the fin structure extend above a top surface of the STI region. The method further includes oxidizing the first fin portion to convert a first material of the first fin portion to a second material. The second material is different from the first material of the first fin portion and a material of the second fin portion. The method further includes forming an oxide layer on the oxidized first fin portion and the second fin portion and forming first and second polysilicon structures on the oxide layer.

Abstract: An electronic device is provided. The electronic device includes a plurality of electronic components and a circuit structure connected to the plurality of electronic components. The circuit structure is configured to connect the electronic components adjacent to each other along a first path, and the circuit structure is further configured to connect the electronic components that are not adjacent to each other along a second path having a greater length and a higher speed than the first path.

Abstract: In one example aspect, a method for integrated circuit (IC) fabrication comprises providing a device structure including a substrate, a source/drain (S/D) feature on the substrate, a gate stack on the substrate, a contact hole over the S/D feature; and a dummy feature over the S/D feature and between the gate stack and the contact hole. The method further comprises forming in the contact hole a contact plug that is electrically coupled to the S/D feature, and, after forming the contact plug, selectively removing the dummy feature to form an air gap that extends higher than a top surface of the gate stack. The method further comprises forming over the contact plug a seal layer that covers the air gap.

Abstract: A method includes attaching a wafer to a wafer chuck having a curved surface. The method further includes placing a device die on the wafer, such that a first dielectric layer of the device die is in contact with a second dielectric layer of the wafer, and performing an annealing process to bond the first dielectric layer to the second dielectric layer. The method further includes encapsulating the device die with an encapsulating material, forming redistribution lines overlapping the encapsulating material and the device die, and sawing the encapsulating material to form a plurality of packages.

Abstract: A battery armor system and method of deploying the same are provided. The battery armor system may comprise one or more sensors configured to detect whether one or more conditions within an environment of a vehicle are met, a moveable skid plate, positioned under a vehicle battery, configured to move between a retracted position and a deployed position, and one or more actuators configured to move the moveable skid plate between the retracted position and the deployed position. In the deployed position, an airgap may be formed between the moveable skid plate and the vehicle battery. The one or more actuators may be configured to move the moveable skid plate into the deployed position upon detection that the one or more conditions are met.

Abstract: A resin composition is provided, which includes a first polymer and a second polymer. The first polymer is formed by a reaction of an epoxy resin modified with a first elastic molecular segment and an epoxy resin curing agent. The second polymer is formed by a polymerization of an acrylate modified with a second elastic molecular segment.

Abstract: A device includes a substrate, a first semiconductor fin over the substrate extending in a first lateral direction, a first vertical stack of semiconductor nanosheets over the substrate extending in the first lateral direction, and an inactive fin between the first semiconductor fin and the first vertical stack extending in the first lateral direction. A first gate structure surrounds and covers the first semiconductor fin, and extends in a second lateral direction substantially perpendicular to the first lateral direction. A second gate structure surrounds and covers the first vertical stack, and extends in the second lateral direction.

Abstract: A liquid cooling rack assembly for a computing system includes a first cabinet rack configured to receive within a plurality of computing devices with heat-generating electronic components; and a second cabinet rack configured to receive coolant components. The second cabinet rack has a plurality of movable trays, each tray of the plurality of movable trays being movable generally horizontally and independently of other trays of the plurality of movable trays. The liquid cooling rack assembly further includes a plurality of cooling pumps. Each pump of the plurality of cooling pumps is placed on a respective one of the plurality of movable trays, and each pump is independently serviceable from other pumps of the plurality of cooling pumps based on independent movement of a respective tray.

Abstract: A task scheduling method includes retrieving at least first data generated by monitoring a plurality of processors and second data generated by monitoring a memory subsystem, generating task type data and processor type data according to at least the first data and the second data, dynamically estimating current capacities and maximum capacities of the plurality of processors according to the task type data and the processor type data, generating prediction data according to the task type data, the processor type data, and the current capacities and the maximum capacities of the plurality of processors, scheduling a task according to the task type data, the processor type data, the prediction data, and the current capacities and the maximum capacities of the plurality of processors.