Patents by Inventor MING-EN BU
MING-EN BU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12190984Abstract: A circuit includes a power management circuit configured to receive at least a first or a second control signal, and to supply at least a first, second or a third supply voltage. The first control signal has a first voltage swing. The second control signal has a second voltage swing. The power management circuit includes a first level shifter circuit configured to generate a first level shifted signal in response to the first control signal, and a first header circuit coupled to at least the first level shifter circuit, a first voltage supply and a second voltage supply. The first header circuit is configured to supply the first supply voltage of the first voltage supply to the first node in response to the first control signal, and to supply the second supply voltage of the second voltage supply to the second node in response to the first level shifted signal.Type: GrantFiled: December 15, 2022Date of Patent: January 7, 2025Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY, LIMITEDInventors: Xiu-Li Yang, Ching-Wei Wu, He-Zhou Wan, Ming-En Bu
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Publication number: 20240371413Abstract: A device includes a virtual power line directly connected to each bitcell in a group of bitcells and a group of transistor switches connected between the virtual power line and a power supply. The device also includes a delay circuit, a first wakeup detector, and a plurality of main input-output (MIO) controllers. The delay circuit is coupled to the gate terminal of each transistor switch of the group of transistor switches. The first wakeup detector is configured to generate a first trigger signal in response to receiving a signal from the delay circuit. The plurality of main input-output (MIO) controllers is configured to be coupled to the power supply through a first group of wakeup switches and through a first group of function switches. A gate terminal of each wakeup switch in the first group of wakeup switches is configured to receive the first trigger signal.Type: ApplicationFiled: July 12, 2024Publication date: November 7, 2024Inventors: He-Zhou WAN, XiuLi YANG, Ming-En BU, Mengxiang XU, Zong-Liang CAO
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Patent number: 12080372Abstract: A device includes a first virtual power line coupled to a power supply through a first group of transistor switches, and a second virtual power line configured to receive the power supply through a second group of transistor switches. The device also includes a delay circuit coupled between the gate terminals of the first group of transistor switches and the gate terminals in the second group of transistor switches. The device further includes a wakeup detector and a plurality of main input-output (MIO) controllers. The wakeup detector is configured to generate a trigger signal after receiving a signal from the output of the delay circuit. The plurality of MIO controllers is coupled to the power supply through a group of wakeup switches and through a group of function switches. The gate terminals in the group of wakeup switches are configured to receive the trigger signal.Type: GrantFiled: December 9, 2022Date of Patent: September 3, 2024Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY, LIMITEDInventors: He-Zhou Wan, Xiuli Yang, Ming-En Bu, Mengxiang Xu, Zong-Liang Cao
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Patent number: 11651134Abstract: A method includes specifying a target memory macro, and determining failure rates of function-blocks in the target memory macro based on an amount of transistors and area distributions in a collection of base cells. The method also includes determining a safety level of the target memory macro, based upon a failure-mode analysis of the target memory macro, from a memory compiler, based on the determined failure rate.Type: GrantFiled: May 28, 2021Date of Patent: May 16, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC CHINA COMPANY, LIMITEDInventors: Ching-Wei Wu, Ming-En Bu, He-Zhou Wan, Hidehiro Fujiwara, Xiu-Li Yang
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Publication number: 20230114646Abstract: A circuit includes a power management circuit configured to receive at least a first or a second control signal, and to supply at least a first, second or a third supply voltage. The first control signal has a first voltage swing. The second control signal has a second voltage swing. The power management circuit includes a first level shifter circuit configured to generate a first level shifted signal in response to the first control signal, and a first header circuit coupled to at least the first level shifter circuit, a first voltage supply and a second voltage supply. The first header circuit is configured to supply the first supply voltage of the first voltage supply to the first node in response to the first control signal, and to supply the second supply voltage of the second voltage supply to the second node in response to the first level shifted signal.Type: ApplicationFiled: December 15, 2022Publication date: April 13, 2023Inventors: Xiu-Li YANG, Ching-Wei WU, He-Zhou WAN, Ming-En BU
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Publication number: 20230105283Abstract: A device includes a first virtual power line coupled to a power supply through a first group of transistor switches, and a second virtual power line configured to receive the power supply through a second group of transistor switches. The device also includes a delay circuit coupled between the gate terminals of the first group of transistor switches and the gate terminals in the second group of transistor switches. The device further includes a wakeup detector and a plurality of main input-output (MIO) controllers. The wakeup detector is configured to generate a trigger signal after receiving a signal from the output of the delay circuit. The plurality of MIO controllers is coupled to the power supply through a group of wakeup switches and through a group of function switches. The gate terminals in the group of wakeup switches are configured to receive the trigger signal.Type: ApplicationFiled: December 9, 2022Publication date: April 6, 2023Inventors: He-Zhou WAN, XiuLi YANG, Ming-En BU, Mengxiang XU, Zong-Liang CAO
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Patent number: 11545191Abstract: A circuit includes a power management circuit and a memory circuit. The power management circuit is configured to receive a first control signal and a second control signal, and to supply a first supply voltage, a second supply voltage and a third supply voltage. The first control signal has a first voltage swing, and the second control signal has a second voltage swing different from the first voltage swing. The first control signal causes the power management circuit to enter a power management mode having a first state and a second state. The memory circuit is coupled to the power management circuit, and is in the first state or the second state in response to at least the first supply voltage supplied by the power management circuit.Type: GrantFiled: February 3, 2021Date of Patent: January 3, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY. LIMITEDInventors: Xiu-Li Yang, Ching-Wei Wu, He-Zhou Wan, Ming-En Bu
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Patent number: 11545192Abstract: A device includes a first virtual power line, a second virtual power line, a first delay circuit, and a first wakeup detector. The first virtual power line and the second virtual power line are coupled to a power supply correspondingly through a first group of transistor switches and a second group of transistor switches. The first delay circuit is coupled between gate terminals of the first group of transistor switches and gate terminals in the second group of transistor switches. The first wakeup detector is configured to generate a first trigger signal after receiving a signal from the first delay circuit.Type: GrantFiled: February 25, 2021Date of Patent: January 3, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY, LIMITEDInventors: He-Zhou Wan, XiuLi Yang, Ming-En Bu, Mengxiang Xu, Zong-Liang Cao
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Publication number: 20220254384Abstract: A device includes a first virtual power line, a second virtual power line, a first delay circuit, and a first wakeup detector. The first virtual power line and the second virtual power line are coupled to a power supply correspondingly through a first group of transistor switches and a second group of transistor switches. The first delay circuit is coupled between gate terminals of the first group of transistor switches and gate terminals in the second group of transistor switches. The first wakeup detector is configured to generate a first trigger signal after receiving a signal from the first delay circuit.Type: ApplicationFiled: February 25, 2021Publication date: August 11, 2022Inventors: He-Zhou WAN, XiuLi YANG, Ming-En BU, Mengxiang XU, Zong-Liang CAO
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Publication number: 20220199124Abstract: A circuit includes a power management circuit and a memory circuit. The power management circuit is configured to receive a first control signal and a second control signal, and to supply a first supply voltage, a second supply voltage and a third supply voltage. The first control signal has a first voltage swing, and the second control signal has a second voltage swing different from the first voltage swing. The first control signal causes the power management circuit to enter a power management mode having a first state and a second state. The memory circuit is coupled to the power management circuit, and is in the first state or the second state in response to at least the first supply voltage supplied by the power management circuit.Type: ApplicationFiled: February 3, 2021Publication date: June 23, 2022Inventors: Xiu-Li YANG, Ching-Wei WU, He-Zhou WAN, Ming-En BU
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Publication number: 20210383052Abstract: A method includes specifying a target memory macro, and determining failure rates of function-blocks in the target memory macro based on an amount of transistors and area distributions in a collection of base cells. The method also includes determining a safety level of the target memory macro, based upon a failure-mode analysis of the target memory macro, from a memory compiler, based on the determined failure rate.Type: ApplicationFiled: May 28, 2021Publication date: December 9, 2021Inventors: Ching-Wei WU, Ming-En BU, He-Zhou WAN, Hidehiro FUJIWARA, Xiu-Li YANG
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Patent number: 11042688Abstract: A method includes specifying a target memory macro with one or more parameters, finding function-blocks in the target memory macro, and determining failure rates of the function-blocks based on an amount of transistors and area distributions in a collection of base cells. The method includes generating a failure-mode analysis for the target memory macro, from a memory compiler, based on the failure rates of the function-blocks. The method includes determining a safety level of the target memory macro, based upon the failure-mode analysis of the target memory macro.Type: GrantFiled: June 9, 2020Date of Patent: June 22, 2021Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC CHINA COMPANY, LIMITEDInventors: Ching-Wei Wu, Ming-En Bu, He-Zhou Wan, Hidehiro Fujiwara, Xiu-Li Yang
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Patent number: 10090032Abstract: A method includes delaying an input voltage signal to generate an output voltage, enabling a capacitor unit to apply across a word line driver a boosted voltage greater than the output voltage, and enabling the word line driver to provide a driving voltage that corresponds to the boosted voltage. A word line driving unit that performs the method and a memory device that includes the word line driving unit are also disclosed.Type: GrantFiled: February 7, 2017Date of Patent: October 2, 2018Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Ming-En Bu, Ching-Wei Wu, He-Zhou Wan, Weiyang Jiang
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Publication number: 20170345473Abstract: A method includes delaying an input voltage signal to generate an output voltage, enabling a capacitor unit to apply across a word line driver a boosted voltage greater than the output voltage, and enabling the word line driver to provide a driving voltage that corresponds to the boosted voltage. A word line driving unit that performs the method and a memory device that includes the word line driving unit are also disclosed.Type: ApplicationFiled: February 7, 2017Publication date: November 30, 2017Inventors: Ming-En Bu, Ching-Wei Wu, He-Zhou Wan, Weiyang Jiang
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Patent number: 9646663Abstract: In some embodiments, a circuit comprises a plurality of memory banks, a column line tracking loop and/or a row line tracking loop, and a tracking circuit. The plurality of memory banks are arranged in a plurality of rows and a plurality of columns of memory building blocks. The column line tracking loop traverses at least a portion of the plurality of rows. The row line tracking loop traverses at least a portion of the plurality of columns. The tracking circuit is configured to receive a first edge of a first signal, cause the first edge of a first signal to be propagated through the column line tracking loop and/or through the row line tracking loop and cause a second edge of the first signal when receiving the propagated first edge of the first signal. The first signal is associated with accessing of the plurality of memory banks.Type: GrantFiled: June 26, 2015Date of Patent: May 9, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ming-En Bu, Xiuli Yang, He-Zhou Wan, Mu-Jen Huang, Jie Cai
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Publication number: 20160358637Abstract: In some embodiments, a circuit comprises a plurality of memory banks, a column line tracking loop and/or a row line tracking loop, and a tracking circuit. The plurality of memory banks are arranged in a plurality of rows and a plurality of columns of memory building blocks. The column line tracking loop traverses at least a portion of the plurality of rows. The row line tracking loop traverses at least a portion of the plurality of columns. The tracking circuit is configured to receive a first edge of a first signal, cause the first edge of a first signal to be propagated through the column line tracking loop and/or through the row line tracking loop and cause a second edge of the first signal when receiving the propagated first edge of the first signal. The first signal is associated with accessing of the plurality of memory banks.Type: ApplicationFiled: June 26, 2015Publication date: December 8, 2016Inventors: MING-EN BU, XIULI YANG, HE-ZHOU WAN, MU-JEN HUANG, JIE CAI
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Patent number: 9490006Abstract: In some embodiments, a time division multiplexing (TDM) circuit is configured to receive an external clock signal and generate an internal clock signal that has at least one pulse during a clock cycle of the external clock signal. An address selector is configured to select a current address before a first time within one of the at least one pulse, and select a next address starting from the first time to generate a selected address. An address storage element is configured to receive the selected address from the address selector and provide a passed through or stored address. The provided address is the current address substantially throughout the one of the at least one pulse. A single-port (SP) memory is configured to access at least one SP memory cell at the address provided by the address storage element in response to the internal clock signal.Type: GrantFiled: February 13, 2015Date of Patent: November 8, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Xiuli Yang, He-Zhou Wan, Ming-En Bu, Mu-Jen Huang, Ching-Wei Wu
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Publication number: 20160163378Abstract: In some embodiments, a time division multiplexing (TDM) circuit is configured to receive an external clock signal and generate an internal clock signal that has at least one pulse during a clock cycle of the external clock signal. An address selector is configured to select a current address before a first time within one of the at least one pulse, and select a next address starting from the first time to generate a selected address. An address storage element is configured to receive the selected address from the address selector and provide a passed through or stored address. The provided address is the current address substantially throughout the one of the at least one pulse. A single-port (SP) memory is configured to access at least one SP memory cell at the address provided by the address storage element in response to the internal clock signal.Type: ApplicationFiled: February 13, 2015Publication date: June 9, 2016Inventors: XIULI YANG, HE-ZHOU WAN, MING-EN BU, MU-JEN HUANG, CHING-WEI WU
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Patent number: 9245615Abstract: A boost system for dual-port SRAM includes a comparator and a boost circuit. The comparator is configured to compare a first row address of a first port and a second row address of a second port, and output a first enable signal. The boost circuit is configured to boost a voltage difference between a first voltage source and a second voltage source according to the first enable signal.Type: GrantFiled: March 19, 2014Date of Patent: January 26, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ching-Wei Wu, He-Zhou Wan, Ming-En Bu, Xiuli Yang, Cheng Hung Lee, Mu-Jen Huang
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Publication number: 20150248928Abstract: A boost system for dual-port SRAM includes a comparator and a boost circuit. The comparator is configured to compare a first row address of a first port and a second row address of a second port, and output a first enable signal. The boost circuit is configured to boost a voltage difference between a first voltage source and a second voltage source according to the first enable signal.Type: ApplicationFiled: March 19, 2014Publication date: September 3, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: CHING-WEI WU, HE-ZHOU WAN, MING-EN BU, XIULI YANG, CHENG HUNG LEE, MU-JEN HUANG