Patents by Inventor Ming Fu Li

Ming Fu Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Schottky barrier source/drain N-MOSFET using ytterbium silicide
    Publication number: 20090179281
    Abstract: An N-type Schottky barrier Source/Drain Transistor (N-SSDT) that uses ytterbium silicide (YbSi2-x) for the source and drain is described. The structure includes a suitable capping layer stack.
    Type: Application
    Filed: February 4, 2009
    Publication date: July 16, 2009
    Inventors: Shiyang Zhu, Jingde Chen, Sungjoo Lee, Ming Fu Li, Jagar Singh, Chungxiang Zhu, Dim-Lee Kwong
  • Schottky barrier source/drain N-MOSFET using ytterbium silicide
    Publication number: 20090163005
    Abstract: A method of fabricating an N-type Schottky barrier Source/Drain Transistor (N-SSDT) with ytterbium silicide (YbSi2-x) for source and drain is presented. The fabrication of YbSi2-x is compatible with the normal CMOS process but ultra-high vacuum, which is required for ErSi2-x fabrication, is not needed here. To prevent oxidation of ytterbium during ex situ annealing and to improve the film quality, a suitable capping layer stack has been developed.
    Type: Application
    Filed: February 9, 2009
    Publication date: June 25, 2009
    Inventors: Shiyang Zhu, Jingde Chen, Sungjoo Lee, Ming Fu Li, Jagar Singh, Chunxiang Zhu, Dim-Lee Kwong
  • Schottky barrier source/drain n-mosfet using ytterbium silicide
    Patent number: 7504328
    Abstract: A method of fabricating an N-type Schottky barrier Source/Drain Transistor (N-SSDT) with ytterbium silicide (YbSi2-x) for source and drain is presented. The fabrication of YbSi2-x is compatible with the normal CMOS process but ultra-high vacuum, which is required for ErSi2-x fabrication, is not needed here. To prevent oxidation of ytterbium during ex situ annealing and to improve the film quality, a suitable capping layer stack has been developed.
    Type: Grant
    Filed: May 10, 2005
    Date of Patent: March 17, 2009
    Assignee: National University of Singapore
    Inventors: Shiyang Zhu, Jingde Chen, Sungjoo Lee, Ming Fu Li, Jagar Singh, Chunxiang Zhu, Dim-Lee Kwong
  • Method of making resonant tunneling diodes and CMOS backend-process-compatible three dimensional (3-D) integration
    Patent number: 7002175
    Abstract: A double barrier resonant tunneling diode (RTD) is formed and integrated with a level of CMOS/BJT/SiGe devices and circuits through processes such as metal-to-metal thermocompressional bonding, anodic bonding, eutectic bonding, plasma bonding, silicon-to-silicon bonding, silicon dioxide bonding, silicon nitride bonding and polymer bonding or plasma bonding. The electrical connections are made using conducting interconnects aligned during the bonding process. The resulting circuitry has a three-dimensional architecture. The tunneling barrier layers of the RTD are formed of high-K dielectric materials such as SiO2, Si3N4, Al2O3, Y2O3, Ta2O5, TiO2, HfO2, Pr2O3, ZrO2, or their alloys and laminates, having higher band-gaps than the material forming the quantum well, which includes Si, Ge or SiGe. The inherently fast operational speed of the RTD, combined with the 3-D integrated architecture that reduces interconnect delays, will produce ultra-fast circuits with low noise characteristics.
    Type: Grant
    Filed: October 8, 2004
    Date of Patent: February 21, 2006
    Assignee: Agency for Science, Technology and Research
    Inventors: Jagar Singh, Yong Tian Hou, Ming Fu Li