Abstract: A system and method for providing a passivation structure for semiconductor devices is provided. In an embodiment, the passivation structure comprises a first barrier layer and a second barrier layer, wherein the second barrier layer may comprise a material, such as cobalt and/or nickel, that is less pure than the first barrier layer. In another embodiment, a single gradient barrier layer is formed. In this embodiment the single gradient barrier layer exhibits a greater pure conductive material, such as cobalt and/or nickel, nearer the conductive line than near the surface.

Abstract: A method of forming an integrated circuit interconnect structure is presented. A first conductive line is formed over a semiconductor substrate. A conductive cap layer is formed on the first conductive line to improve device reliability. An etch stop layer (ESL) is formed on the conductive cap layer. An inter-level dielectric (IMD) is formed on the ESL. A via opening and a trench are formed in the ESL, IMD, and conductive cap layer. A recess is formed in the first conductive line. The recess can be formed by over etching when the first dielectric is etched, or by a separate process such as argon sputtering. A second conductive line is formed filling the trench, opening and recess.

Abstract: A chemical solution for an electro chemical plating process includes an electro chemical plating solution; and an additive, added in the electro chemical plating solution, substantially consisting of a polymer with one or more kinds of impurities, wherein each kind of the impurities has a density, with respect to the polymer, lower then 1019 atoms/cc.

Abstract: A method of forming a copper filled semiconductor feature having improved bulk properties including providing a semiconductor process wafer having a process surface including an opening for forming a semiconductor feature; depositing at least one metal dopant containing layer over the opening to form a thermally diffusive relationship to a subsequently deposited copper layer; depositing said copper layer to substantially fill the opening; and, thermally treating the semiconductor process wafer for a time period sufficient to distribute at least a portion of the metal dopants to collect along at least a portion of the periphery of said copper layer including a portion of said copper layer grain boundaries.

Abstract: A new method is provided that allows for the application of electropolish for removal of copper and that is independent of pattern density of the removed copper. Electropolish of the copper is first accomplished by reversing current in the H2SO4 or H3PO4 solution. After identifying the endpoint of the electropolish, chemical etching of the copper in a H2SO4 or H3PO4 solution is continued, in this manner avoiding effects of high current density introduced by pattern density.

Abstract: A composition and method which substantially enhances the wetting of an electrolyte solution to a surface in the electrochemical plating of a metal such as copper on the surface. The composition is an organic mixture which includes an organic acid, such as citric acid or acetic acid, and a low molecular weight ionic polymer such as an alcohol, an amine or alkyphenol alkoxylate. The method includes suspending the composition as a layer in the solution and passing the surface through the composition suspension layer to define a wetting layer on the surface. Consequently, metal electroplated onto the surface is substantially devoid of pits or other structural defects.

Abstract: A composition and method which is suitable to enhance the wetting of an electroplating bath solution on an electroplating surface. Optimum wetting of the electroplating bath solution to the electroplating surface results in an electroplated metal which is substantially devoid of surface pits and other structural defects and is characterized by enhanced gap fill capability. The composition includes a suppressor additive for the electroplating bath solution. The suppressor additive is a copolymer which includes various proportions of ethylene oxide monomer and propylene oxide monomer.

Abstract: A new processing sequence is provided for the creation of a metal gate electrode. At least two polysilicon gate electrodes are provided over the surface of a substrate, these polysilicon gate electrodes having a relatively thick layer of gate dielectric making these polysilicon gate electrodes suitable for high-voltage applications. The two polysilicon gate electrodes are divided into a first and a second gate electrode, both gate electrodes are imbedded in a layer of Intra Metal Dielectric (IMD). The first gate electrode is removed by applying a lift-off process to this first gate electrode, creating an opening in the layer of IMD. The second gate structure is shielded by a photoresist mask during the removal of the first gate electrode. A metal gate electrode is created in the opening created in the layer of IMD, using a thin layer of gate dielectric.

Abstract: A method for reducing or avoiding copper layer pitting in a copper electrochemical deposition process to improve deposition uniformity including providing a substrate for carrying out at least a first copper electroplating process; providing a copper electroplating solution including a deforming (antiforming) agent wherein the antiforming (deforming) agent includes at least one alkylene monomer; and, carrying out at least a first copper electroplating process to deposit at least a first copper layer.

Abstract: A new method is provided that allows for the application of electropolish for removal of copper and that is independent of pattern density of the removed copper. Electropolish of the copper is first accomplished by reversing current in the H2SO4 or H3PO4 solution. After identifying the endpoint of the electropolish, chemical etching of the copper in a H2SO4 or H3PO4 solution is continued, in this manner avoiding effects of high current density introduced by pattern density.

Abstract: A new processing sequence is provided for the creation of a metal gate electrode. At least two polysilicon gate electrodes are provided over the surface of a substrate, these polysilicon gate electrodes having a relatively thick layer of gate dielectric making these polysilicon gate electrodes suitable for high-voltage applications. The two polysilicon gate electrodes are divided into a first and a second gate electrode, both gate electrodes are imbedded in a layer of Intra Metal Dielectric (IMD). The first gate electrode is removed by applying a lift-off process to this first gate electrode, creating an opening in the layer of IMD. The second gate structure is shielded by a photoresist mask during the removal of the first gate electrode. A metal gate electrode is created in the opening created in the layer of IMD, using a thin layer of gate dielectric.

Abstract: A cleaning apparatus for an ECMD anode pad including a vacuum head which applies vacuum pressure to the surface of the anode pad between ECMD operations in order to remove particles precipitated onto the surface of the anode pad and prevent or minimize inadvertent scratching or peeling of a wafer supported by the pad during the process. The particles are dislodged from the anode pad and removed from the ECMD system by flow of electrolyte solution into the vacuum head. The electrolyte solution is typically filtered before returning to the electrolyte tank for ultimate redistribution to the ECMD system.

Abstract: A method and apparatus for monitoring copper seed layer growth during copper plating of a semiconductor wafer. A ring contact for use in copper plating of the semiconductor wafer is generally divided into a plurality of switches thereof. The ring contact is biased to prior to copper plating of the semiconductor wafer to determine a copper seed layer conductivity. Each switch among the plurality of switches can be connected together and thereafter the switches may be biased to an anode during copper plating, thereby permitting in-situ monitoring of copper seed resistance prior to the copper plating and a detection of copper seed damage and copper seed corrosion associated with the copper plating.

Abstract: A method of forming a protective layer included in a metal filled semiconductor feature including providing a substrate including an insulating dielectric material having an anisotropically etched opening for forming a semiconductor feature; conformally depositing over the semiconductor feature at least one metal layer to substantially fill the semiconductor feature at least a portion of the at least one metal layer containing dopant impurities; and, thermally treating the substrate for a time period sufficient to redistribute the dopant impurities to preferentially collect along the periphery of the at least one metal layer.