Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.

Abstract: In an embodiment, a structure includes: a first integrated circuit die including first die connectors; a first dielectric layer on the first die connectors; first conductive vias extending through the first dielectric layer, the first conductive vias connected to a first subset of the first die connectors; a second integrated circuit die bonded to a second subset of the first die connectors with first reflowable connectors; a first encapsulant surrounding the second integrated circuit die and the first conductive vias, the first encapsulant and the first integrated circuit die being laterally coterminous; second conductive vias adjacent the first integrated circuit die; a second encapsulant surrounding the second conductive vias, the first encapsulant, and the first integrated circuit die; and a first redistribution structure including first redistribution lines, the first redistribution lines connected to the first conductive vias and the second conductive vias.

Abstract: Some embodiments of the present disclosure relate to an integrated chip including an extended via that spans a combined height of a wire and a via and that has a smaller footprint than the wire. The extended via may replace a wire and an adjoining via at locations where the sizing and the spacing of the wire are reaching lower limits. Because the extended via has a smaller footprint than the wire, replacing the wire and the adjoining via with the extended via relaxes spacing and allows the size of the pixel to be further reduced. The extended via finds application for capacitor arrays used for pixel circuits.

Abstract: The accumulated oil separator has a main body with an oil-gas connecting pipe on its front end and with an axial central hole having a predetermined diameter: a through hole in the main body is concentric with an axial central hole of the oil-gas connecting pipe; a radially extending chamber is extended down a predetermined depth from the top of the main body and is communicated on its two lateral sides with the axial central hole and the through hole; a regulatory controlling means is mounted in the radial chamber to control normal oil filling and oil-gas recovery, or can be regulated to be in an accumulated oil removing state; an accumulated oil discharging outlet is formed by drilling to communicate transversely with the radial chamber; the regulatory controlling means can directly discharge accumulated oil from the oil-gas recovery system for collection when it is adjusted to discharge accumulated oil.

Abstract: A method determines the deficient processes and deficient processing stations in the manufacture of a product fabricated by lots through a plurality of processes performed by a plurality of processing stations. From a plurality of lots, the good lots are distinguished from the bad lots. By using the process history of each good and bad lot, a good lot ratio and a bad lot ratio that are respectively produced by each process performed by one of the processing stations are calculated. The processes/processing stations are arranged according to a decreasing order of their bad lot ratios. The most probable deficient processes/processing stations are those which are arranged at the top of the arranged order.

Abstract: A method of removing photoresist at the edge of waters in an integrated circuit the method comprising the following steps. A substrate having at least a MOS component region thereabove is provided. A photoresist layer is formed over the substrate. A pattern is defined on the photoresist layer by exposure and development. The photoresist layer at the edge of the substrate is removed by a chemical reagent and centrifugal effect.

Abstract: Dielectric structures of the type that might be used in DRAMs, other memory devices, and integrated thin film transistors include repeated silicon oxide/silicon nitride layers. For example, the dielectric structure may have a silicon oxide/silicon nitride/silicon oxide/silicon nitride/silicon oxide or "ONONO" layer structure. Such repeated layer structures exhibit higher levels of breakdown voltage than more conventional "ONO" structures. Most of the growth of the five layer ONONO or more complicated dielectric structure can be accomplished in a single furnace through a series of temperature steps performed under different gas ambients. A substrate having a polysilicon lower electrode is introduced to a furnace and a lowest layer of silicon oxide is grown on the polysilicon electrode in an ammonia ambient. A first silicon nitride layer is grown in NH.sub.3 and SiH.sub.2 Cl.sub.

Abstract: A method of forming a self-aligned contact of a DRAM cell includes providing a substrate having a MOS transistor. The MOS transistor includes a gate and a source/drain region. A first insulating layer, a second insulating layer and a third insulating layer are formed over the surface of the substrate in succession. The third insulating layer is planarized. A contact window mask is formed above the third insulating layer. Using the contact window mask as a cover, the third insulating layer is removed using anisotropic dry etching and isotropic wet etching. Then, a portion of the second insulating layer and a portion of the first insulating layer are removed sequentially to expose the source/drain region so that a self-aligned contact is formed.

Abstract: A lightly doped drain (LDD) metal oxide semiconductor field effect transistor (MOSFET). Field oxide is used as a hard mask for a total-overlap polysilicon (TOP) gate which minimizes hot-carrier degradation, so that a soft-mask step is saved. The field oxide is used also as a hard mask for surface counter-doping which reduces gate-induced drain leakage, and in making a punch-through stop which reduces drain-induced barrier low and short channel effect.

Abstract: Disclosed is a method of forming self-aligned buried contact implementing self-alignment technology into buried contact process to prevent failure of semiconductor elements due to disconnection of wiring which is caused by misalignment. This is done by forming a sidewall spacer in the recess on the buried contact region. The tolerance of misalignment is greatly increased because a polysilicon layer will contact with the buried contact region if the polysilicon layer could contact the sidewall spacer.

Abstract: An improved process for fabricating a planar field oxide structure on a silicon substrate was achieved. The process involves forming the field oxide by using the LOCal Oxidation of Silicon (LOCOS) process in which the device area is protected from oxidation by a silicon nitride layer. A sacrificial leveling layer, such as spin-on-glass (SOG) or a anti-reflective coating (ARC) layer is used to fill in the gap between the silicon nitride and the field oxide structure and make more planar the substrate surface. The leveling layer is then etched back non-selectively by plasma etching to planarize the portion of the field oxide extending above the substrate surface. The method does not require a recess to be etched in the silicon substrate and therefore, has certain reliability and cost advantages.

Abstract: An improved process for fabricating a planar field oxide structure on a silicon substrate was achieved. The process involves forming the field oxide by using the LOCal Oxidation of Silicon (LOCOS) process in which the device area is protected from oxidation by a silicon nitride layer. A sacrificial implant layer, such as CVD oxide, oxynitride or an anti-reflective coating (ARC) layer is used to fill in the gap between the silicon nitride and the field oxide structure and make more planar the substrate surface. The substrate surface is then implanted with As.sup.75 or p.sup.31 ions penetrating the sacrificial implant layer and forming a implant damaged layer on the field oxide. The implant damaged layer which etches faster in a wet etch in removed selectively thereby making a more planar field oxide structure. The method does not require a recess to be etched in the silicon substrate and therefore, has certain reliability and cost advantages.