Abstract: A display panel includes a liquid crystal cell, a first polarizing assembly and a second polarizing assembly. The liquid crystal cell includes a first substrate and a second substrate disposed opposite to each other, and a liquid crystal layer disposed between the first substrate and the second substrate. The first polarizing assembly is disposed on a side of the first substrate further away from the liquid crystal layer and includes at least a first polarizing layer having a first transmission axis, and the first polarizing assembly is configured for generating polarized light whose polarization direction is parallel to the first transmission axis. The second polarizing assembly is located on a side of the second substrate further away from the liquid crystal layer and includes at least a transflective layer and a light absorbing layer.

Abstract: Embodiments of the present disclosure provide a display module and a preparation method therefor, and a display apparatus. The display module includes a liquid crystal display panel and a light scattering layer. Among them, the liquid crystal display panel includes a first substrate, a second substrate, and a first liquid crystal layer, the first substrate is disposed opposite to the second substrate, the first liquid crystal layer is located between the first substrate and the second substrate, and the first liquid crystal layer includes a cholesteric liquid crystal configured to have a conical helix texture when an electric field is applied, to reflect light matched with a helical pitch of the conical helix texture; and the light scattering layer is disposed on a side of the liquid crystal display panel and is configured to scatter light reflected by the liquid crystal display panel.

Abstract: The present invention discloses a base unit and a desktop cooling fan having the base unit, wherein the base unit comprises a base for detachably carrying a front panel unit, and/or a cooling unit, and/or an air supply unit mounting part, and/or a cover unit, and/or a refrigerant unit, and the base is formed with a lower liquid storage tank structure which can be closed. This freely disassembled and assembled structure provides flexible and convenient use performance. Meanwhile, the cooling device provided also effectively overcomes the problems of easy discoloration, aging, high noise, easy overflow of a refrigerant medium in use of the wet curtain of the existing apparatus.

Abstract: A scan-based self-test architecture and method using weighted scan enable signals is disclosed. The self-test architecture comprises: a linear feedback shift register; a phase shifter connected to outputs of the linear feedback shift register, and scan chains and the combinational part of the circuit under test; an AND gate; scan chains, each being formed by serially connecting multiple scan flip-flops having the same architecture; a multiplexer; and a logic unit for generating weighted random signal, whose inputs are connected with the phase shifter; the logic unit randomly selects the input pseudo random signals, weights the selected pseudo random signals, and assigns the weighted pseudo random signals assigned to the scan enable signals of the scan chains, to control the switching of the scan chains between the scan shift mode and the functional mode. The test effectiveness of scan-based BIST can be improved greatly using the test scheme with weighted scan enable signals.

Abstract: A scan-based self-test architecture and method using weighted scan enable signals is disclosed. The self-test architecture comprises: a linear feedback shift register; a phase shifter connected to outputs of the linear feedback shift register, and scan chains and the combinational part of the circuit under test; an AND gate; scan chains, each being formed by serially connecting multiple scan flip-flops having the same architecture; a multiplexer; and a logic unit for generating weighted random signal, whose inputs are connected with the phase shifter; the logic unit randomly selects the input pseudo random signals, weights the selected pseudo random signals, and assigns the weighted pseudo random signals assigned to the scan enable signals of the scan chains, to control the switching of the scan chains between the scan shift mode and the functional mode. The test effectiveness of scan-based BIST can be improved greatly using the test scheme with weighted scan enable signals.

Abstract: A method and apparatus for scan design architecture with non-scan testing cost is disclosed. In one embodiment, the method comprises: transforming a plurality of sequential cells for a sequential circuit to a plurality of controllable and observable cells for a combinational circuit; connecting said plurality of sequential cells with at least one shifter registers; obtaining at least one scan chains; and substituting the ATPG step for said sequential circuit with the ATPG for said combinational circuit. In another embodiment, the apparatus comprises: means for transforming a plurality of sequential cells for a sequential circuit to a plurality of controllable and observable cells for a combinational circuit; means for connecting said plurality of sequential cells with at least one shifter registers; means for obtaining at least one scan chains; and means for substituting the ATPG step for said sequential circuit with the ATPG for said combinational circuit.

Abstract: A method and apparatus for scan design architecture with non-scan testing cost is disclosed. In one embodiment, the method comprises: transforming a plurality of sequential cells for a sequential circuit to a plurality of controllable and observable cells for a combinational circuit; connecting said plurality of sequential cells with at least one shifter registers; obtaining at least one scan chains; and substituting the ATPG step for said sequential circuit with the ATPG for said combinational circuit. In another embodiment, the apparatus comprises: means for transforming a plurality of sequential cells for a sequential circuit to a plurality of controllable and observable cells for a combinational circuit; means for connecting said plurality of sequential cells with at least one shifter registers; means for obtaining at least one scan chains; and means for substituting the ATPG step for said sequential circuit with the ATPG for said combinational circuit.