Abstract: This application discloses a communications chip structure, including: a channel selection module, configured to receive an input signal, where the input signal is a signal of a preset narrow bandwidth span or a signal of a preset wide bandwidth span; and a digital baseband module, configured to control the channel selection module to select a first sampling and quantification channel when the input signal is a signal of the preset narrow bandwidth span, or control the channel selection module to select a second sampling and quantification channel when the input signal is a signal of the preset wide bandwidth span. The channel selection module is further configured to send the input signal to the first sampling and quantification channel or the second sampling and quantification channel for sampling and quantification.

Abstract: This application discloses a communications chip structure, including: a channel selection module, configured to receive an input signal, where the input signal is a signal of a preset narrow bandwidth span or a signal of a preset wide bandwidth span; and a digital baseband module, configured to control the channel selection module to select a first sampling and quantification channel when the input signal is a signal of the preset narrow bandwidth span, or control the channel selection module to select a second sampling and quantification channel when the input signal is a signal of the preset wide bandwidth span. The channel selection module is further configured to send the input signal to the first sampling and quantification channel or the second sampling and quantification channel for sampling and quantification.

Abstract: The present invention relates to an analog to digital converter. The analog to digital converter includes comparing modules at multi levels, where a comparing module at each level includes a comparator and a metastable state determining unit. The comparator is configured to, when a previous-level comparing module is not in a metastable state, receive a first clock, a first input signal, and a second input signal, and compare the first input signal with the second input signal. The metastable state determining unit is configured to, when the previous-level comparing module is not in a metastable state, receive the first clock, generate a reference clock according to the first clock, and if a second clock that is output by the comparator is later than the reference clock, determine that the current-level comparing module is in a metastable state.

Abstract: The present invention relates to an analog to digital converter. The analog to digital converter includes comparing modules at multi levels, where a comparing module at each level includes a comparator and a metastable state determining unit. The comparator is configured to, when a previous-level comparing module is not in a metastable state, receive a first clock, a first input signal, and a second input signal, and compare the first input signal with the second input signal. The metastable state determining unit is configured to, when the previous-level comparing module is not in a metastable state, receive the first clock, generate a reference clock according to the first clock, and if a second clock that is output by the comparator is later than the reference clock, determine that the current-level comparing module is in a metastable state.