Abstract: A three-dimensional (3D) memory device and a method for forming the same are disclosed. In certain aspects, the 3D memory device includes a stack including interleaved conductive layers and dielectric layers, and a channel structure extending through the stack in a first direction. The channel structure includes a memory film and a semiconductor channel that exceeds the memory film in the first direction, and the memory film surrounds the semiconductor channel. An adhesive layer is disposed on and in contact with the semiconductor channel that exceeds the memory film. A conductor layer is disposed on and in contact with the adhesive layer.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure and a second semiconductor bonded with the first semiconductor structure. The first semiconductor structure includes an array of NAND memory strings, a semiconductor layer in contact with source ends of the array of NAND memory strings, an insulating layer in contact with the semiconductor layer, and a contact structure in the insulating layer. The insulating layer electrically insulates the contact structure from the semiconductor layer. The second semiconductor structure includes a transistor.

Abstract: In some aspects, a package structure includes a substrate and semiconductor devices stacked over the substrate. The semiconductor devices are stacked along a first direction, and at least one of the semiconductor devices comprises one or more pads located on a side surface of the at least one of the semiconductor devices.

Abstract: Semiconductor structures, forming methods thereof and semiconductor devices are provided. In one aspect, a semiconductor structure includes: a stack structure, a semiconductor layer on the stack structure, a channel structure extending through the stack structure and into the semiconductor layer, a contact structure extending along a stacking direction of the stack structure, and a first soldering structure and a second soldering structure. The first soldering structure penetrates through the semiconductor layer and is connected with the contact structure and the second soldering structure is connected with the semiconductor layer.

Abstract: In one example, a semiconductor device includes a conductive layer, composite structures, conductive posts and first pads. The composite structures may be located on the conductive layer and stacked in a direction perpendicular to the plane in which the conductive layer is located. The composite structure may include a chip, an insulating layer surrounding around the chip, and at least one second pad electrically connected with the chip. The second pad is located on the insulating layer. The second pads of the composite structures are at different locations in the first direction. The first direction is perpendicular to the thickness direction of the composite structures. The conductive posts are located in the insulating layer of the composite structures and each conductive post is connected with one of the second pads and one of the first pads.

Abstract: A three-dimensional (3D) memory device and methods for forming the same are provided. The 3D memory device includes a first semiconductor structure having a core region and a non-array region. The first semiconductor structure includes: an array of channel structures in the core region; a substrate layer extending from the non-array region to the core region and being in contact with the array of channel structures; an insulating structure including a first portion extending along a lateral direction from the non-array region to the core region and a second portion extending along a vertical direction through the substrate layer in the non-array region, where the second portion of the insulating structure surrounds the core region; and contact structures penetrating through the second portion of the insulating structure, where the contact structures are electrically insulated from the substrate layer by the insulating structure.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In one example, a 3D memory device includes a multi-layer stacked structure, where the multi-layer stacked structure includes a plurality of alternately stacked conductive layers and dielectric layers. The 3D memory device further includes a semiconductor layer over the multi-layer stacked structure, and a plurality of channel structures penetrating into the multi-layer stacked structure and the semiconductor layer. A first end of each channel structure is located within the semiconductor layer, and the first ends of the channel structures are aligned with one another.

Abstract: Aspect of the disclosure provide a semiconductor device including a stack structure having a core region in which a plurality of channel structures are formed, and a semiconductor layer located on one side of the stack structure in a stacking direction of the stack structure, the channel structures extending to the semiconductor layer, and projections of the semiconductor layer and the channel structures in a plane parallel to the stacking direction not overlapping. The semiconductor device can further include a first insulating layer at least located on a first surface of the semiconductor layer far away from the stack structure, and a first leading-out portion penetrating through a portion of the first insulating layer corresponding to the core region in the stacking direction and being in contact with the semiconductor layer.

Abstract: A method for suppressing magnetizing inrush current of the transformer with flux linkage control includes connecting a small-capacity direct current/alternating current (DC/AC) converter with the secondary winding or auxiliary winding of transformer, detecting the primary side phase voltage before closing load, inducing the core flux linkage reference according to the relationship between the winding voltage and core flux linkage. The core flux linkage closed-loop PI control system is constructed to control the converter voltage in the synchronous coordinate, then the core flux linkage can track its reference with no static error, thus the sinusoidal flux linkage with 90-degree difference from the grid voltage can be pre-established in the core before no-load closing. By these methods, no matter when the main transformer closes, the core flux linkage is always in the steady state, and the magnetizing inrush current can be eliminated completely.

Abstract: Aspects of the disclosure provide a semiconductor device and a method to fabricate the semiconductor device. The semiconductor device includes a first die comprising a first contact structure formed on a face side of the first die. The semiconductor device includes a first semiconductor structure and a first pad structure that are disposed on a back side of the first die. The first semiconductor structure is conductively connected with the first contact structure from the back side of the first die and the first pad structure is conductively coupled with the first semiconductor structure. An end of the first contact structure protrudes into the first semiconductor structure without connecting to the first pad structure. The first die and a second die can be bonded face-to-face.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure and a second semiconductor bonded with the first semiconductor structure. The first semiconductor structure includes an array of NAND memory strings, a semiconductor layer in contact with source ends of the array of NAND memory strings, an insulating layer in contact with the semiconductor layer, and a contact structure in the insulating layer. The insulating layer electrically insulates the contact structure from the semiconductor layer. The second semiconductor structure includes a transistor.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure and a second semiconductor structure bonded with the first semiconductor structure. The first semiconductor structure includes an array of NAND memory strings, a semiconductor layer in contact with source ends of the array of NAND memory strings, a non-conductive layer aligned with the semiconductor layer, and a contact structure in the non-conductive layer. The non-conductive layer electrically insulates the contact structure from the semiconductor layer. The second semiconductor structure includes a transistor.

Abstract: A magnetic integrated hybrid distribution transformer includes a main transformer, a series isolation transformer and a converter, wherein: an iron core includes an iron beam unit, an iron yoke unit and a leakage magnetic core unit. The main transformer includes secondary windings, primary windings and control windings all of which are layer-windings and wound around main transformer iron beams. The series isolation transformer includes converter side windings and grid side windings all of which are pancake-windings and wound around isolation transformer iron beams. The converter side windings and the control windings are respectively connected with the converter by the star connection with neutral point. Leakage magnetic cores are respectively inserted between the primary windings and the control windings or between the converter side windings and the grid side windings, so as to achieve magnetic integration design of the transformer and output connection inductor of the converter.

Abstract: A method for suppressing magnetizing inrush current of the transformer with flux linkage control includes connecting a small-capacity direct current/alternating current (DC/AC) converter with the secondary winding or auxiliary winding of transformer, detecting the primary side phase voltage before closing load, inducing the core flux linkage reference according to the relationship between the winding voltage and core flux linkage. The core flux linkage closed-loop PI control system is constructed to control the converter voltage in the synchronous coordinate, then the core flux linkage can track its reference with no static error, thus the sinusoidal flux linkage with 90-degree difference from the grid voltage can be pre-established in the core before no-load closing. By these methods, no matter when the main transformer closes, the core flux linkage is always in the steady state, and the magnetizing inrush current can be eliminated completely.

Abstract: A magnetic integrated hybrid distribution transformer includes a main transformer, a series isolation transformer and a converter, wherein: an iron core includes an iron beam unit, an iron yoke unit and a leakage magnetic core unit. The main transformer includes secondary windings, primary windings and control windings all of which are layer-windings and wound around main transformer iron beams. The series isolation transformer includes converter side windings and grid side windings all of which are pancake-windings and wound around isolation transformer iron beams. The converter side windings and the control windings are respectively connected with the converter by the star connection with neutral point. Leakage magnetic cores are respectively inserted between the primary windings and the control windings or between the converter side windings and the grid side windings, so as to achieve magnetic integration design of the transformer and output connection inductor of the converter.