Abstract: A hierarchical system firewall, comprising a root security manager, secondary security managers, a firewall controller, and firewalls. The root security manager designates a secondary security manager and allocates a system resource for each domain cluster, and provides firewall configuration schemes between the domain clusters. The secondary security managers add domain identifiers for hosts and devices of domain clusters, and provides a firewall configuration scheme for each domain. The firewall controller adds domain cluster identifiers for the hosts and devices in the system, and adds identification for the secondary security managers; allocates domain identification for a host and a device of a current domain cluster; and configures access permissions for the firewall of each device in the current domain cluster. The firewalls perform permissions control for access to a current device by hosts from different domains or different domain clusters.

Abstract: A hierarchical system firewall, comprising a root security manager, secondary security managers, a firewall controller, and firewalls. The root security manager designates a secondary security manager and allocates a system resource for each domain cluster, and provides firewall configuration schemes between the domain clusters. The secondary security managers add domain identifiers for hosts and devices of domain clusters, and provides a firewall configuration scheme for each domain. The firewall controller adds domain cluster identifiers for the hosts and devices in the system, and adds identification for the secondary security managers; allocates domain identification for a host and a device of a current domain cluster; and configures access permissions for the firewall of each device in the current domain cluster. The firewalls perform permissions control for access to a current device by hosts from different domains or different domain clusters.

Abstract: A camera interface circuit for a barcode scanner includes a binary conversion block and a selection module. The binary conversion block receives image signals from a camera, and converts gray levels of each pixel in each image frame into binary codes. The selection module alternately provides binary codes of one image frame and image signals of a consecutive image frame as outputs.

Abstract: A camera interface circuit for a barcode scanner includes a binary conversion block and a selection module. The binary conversion block receives image signals from a camera, and converts gray levels of each pixel in each image frame into binary codes. The selection module alternately provides binary codes of one image frame and image signals of a consecutive image frame as outputs.

Abstract: A method of encrypting data on a memory device includes receiving a memory transaction request at an inline encryption engine coupled between a processing core and switch fabric in a system on a chip (SOC). The memory transaction request includes a context component and a data component. The context component is analyzed to determine whether the data component will be stored in an encrypted memory region. If the data component will be stored in an encrypted memory region, the data component is encrypted and communicated to a location in the encrypted memory region. The location is based at least on the context component.

Abstract: A controller for a persistent display device has an overall table of waveform data corresponding to different transitions of pixels from all pixel states to all others for differing operating parameters. A hardware LUT module receives input values containing new and current pixel state data and indexes to identify update requests, stores in LUT table memory space mapping values that are segments of waveform data generated in run time according to the operating parameters of each update request, and places segments of waveform data corresponding to the update requests into LUT output memory space. A SIMD module transposes waveform data of the update requests from the LUT output memory space, and places the transposed waveform data in respective frame scan buffers. An interface receives the transposed waveform data for the display device to update an image displayed on the panel.

Abstract: A method for conserving power in a computing device having a volatile system memory, a non-volatile storage device, and a processor executing an operating system and including an internal non-volatile memory (NVM). The method includes receiving, at the processor, a request to enter the computing device into a hibernation mode, suspending, by the processor, execution of the operating system, copying, by the processor, substantially the entire contents of the volatile system memory into the non-volatile storage device, storing, in the internal NVM of the processor, a hibernate flag, and turning off power to the computing device.

Abstract: A method of encrypting data on a memory device includes receiving a memory transaction request at an inline encryption engine coupled between a processing core and switch fabric in a system on a chip (SOC). The memory transaction request includes a context component and a data component. The context component is analyzed to determine whether the data component will be stored in an encrypted memory region. If the data component will be stored in an encrypted memory region, the data component is encrypted and communicated to a location in the encrypted memory region. The location is based at least on the context component.

Abstract: A data processing system includes a boot read only memory (ROM) configured to store boot code; one time programmable (OTP) storage circuitry configured to store patch instructions; a random access memory (RAM); and a processor coupled to the boot ROM, the OTP storage circuitry, and the RAM. The processor is configured to: in response to a reset of the data processing system, copy one or more patch instructions from the OTP storage circuitry into the RAM, and during execution of the boot code, execute a patch instruction from the RAM in place of a boot instruction of the boot code.

Abstract: A semiconductor device includes a processing system including a section of power domain circuitry and a section of coin cell power domain circuitry. The coin cell power domain circuitry is configured to, when power is initially provided to the coin cell power domain circuitry, using power provided by a power management circuit as feedback to determine that the power management circuit provides the power in response to a power request signal being a toggle signal, and determine that the power management circuit provides the power in response to the power request signal being a pulse signal.

Abstract: A controller for a persistent display device has an overall table of waveform data corresponding to different transitions of pixels from all pixel states to all others for differing operating parameters. A hardware LUT module receives input values containing new and current pixel state data and indexes to identify update requests, stores in LUT table memory space mapping values that are segments of waveform data generated in run time according to the operating parameters of each update request, and places segments of waveform data corresponding to the update requests into LUT output memory space. A SIMD module transposes waveform data of the update requests from the LUT output memory space, and places the transposed waveform data in respective frame scan buffers. An interface receives the transposed waveform data for the display device to update an image displayed on the panel.

Abstract: A display device has a display controller and a persistent display panel for displaying static images. The display controller has a pre-processor that extracts data for updating a frame of the display from a memory module storing display data and compresses the data. A frame buffer stores the compressed data. A display driver receives and de-compresses the compressed data from the frame buffer and repeatedly refreshes the display panel while updating the displayed frame.

Abstract: A data processing system includes a boot read only memory (ROM) configured to store boot code; one time programmable (OTP) storage circuitry configured to store patch instructions; a random access memory (RAM); and a processor coupled to the boot ROM, the OTP storage circuitry, and the RAM. The processor is configured to: in response to a reset of the data processing system, copy one or more patch instructions from the OTP storage circuitry into the RAM, and during execution of the boot code, execute a patch instruction from the RAM in place of a boot instruction of the boot code.

Abstract: A semiconductor device includes a processing system including a section of power domain circuitry and a section of coin cell power domain circuitry. The coin cell power domain circuitry is configured to, when power is initially provided to the coin cell power domain circuitry, using power provided by a power management circuit as feedback to determine that the power management circuit provides the power in response to a power request signal being a toggle signal, and determine that the power management circuit provides the power in response to the power request signal being a pulse signal.