Abstract: The present disclosure is directed to a device having a coating or liner of a polymer material that may significantly improve the mechanical performance and stability of through hole via interconnects, such as through glass vias interconnects, by damping the stresses from the expansion of copper used as a conductive material. The present lining method for the through hole vias uses selected polymers that have a low-viscosity and may be capable of in-situ polymerization, i.e., curing, after being placed in the through hole vias.

Abstract: Microelectronic integrated circuit package structures include a package structure comprising a plurality of metal vias and a layer of glass surrounding the metal vias. The layer of glass has a first side and a second side opposite the first side, where the metal vias extend between the first side and the second side of the layer of glass. An edge sidewall is between the first side and the second side and defines a perimeter of the first side, the perimeter comprising four corners and the edge sidewall having a non-linear path from a first corner to a second corner of the four corners.

Abstract: A method for real-time offset adjustment of a semiconductor die placement comprising: obtaining or receiving operational parameters of a die mounting tool in real-time, wherein the die mounting tool is configured for placing the semiconductor die on a panel; predicting an offset adjustment of the semiconductor die placement based on the operational parameters; and determining semiconductor die placement coordinates based on an original die placement and the offset adjustment.

Abstract: An apparatus comprises a glass core comprising a top surface and a bottom surface opposite the top surface. A plurality of vias extending between the top and bottom surfaces. A metallization layer is over at least a portion of the top surface. An edge is between the top and bottom surfaces. The edge comprises one or more protrusions or one or more cavities. Each of the protrusions or cavities comprises a first surface parallel to the top surface, a second surface non-parallel to the top surface, and a polymer or a metal on the first or second surface.

Abstract: Hybrid glass and organic substrates, devices and systems formed thereon, and methods of forming the same, are disclosed herein. In one example, a substrate includes a glass layer and an organic frame around the glass layer, where the organic frame includes a polyimide.

Abstract: A method for recognizing a reference point associated with a fiducial marker including the steps of: obtaining or receiving image data of the fiducial marker; determining the degree of which the image data of the fiducial marker is aligned with one or more reference images; of which if the degree of alignment is determined to be less than an acceptable threshold predicting a set of coordinates of the reference point associated with the fiducial marker; incorporating the set of coordinates with the image data to form a modified image data; and determining the degree of which the modified image data of the fiducial marker is aligned with one or more reference images.

Abstract: Multi-die bridge assemblies and methods for three-dimensional packaging. The architectures assemble a bridge component with two or more integrated circuit die to thereby create a multi-die (MD) bridge assembly. The means for attaching the bridge component to the dies can be hybrid bonding, solder bumps, thermal compression bonding, or a combination thereof. The created MD bridge assembly can be subjected to performance testing prior to attachment to a substrate. Attaching the MD bridge assembly to the substrate can include fitting the bridge component portion into a cavity in the substrate and attaching the bridge component to a cavity floor with another plurality of attachment options.

Abstract: Example methods and apparatus for embedding interconnect bridges having through silicon vias in substrates are disclosed. An example semiconductor package a bridge die disposed in a recess of an underlying substrate, the bridge die including a via that electrically couples a first contact on a first side of the bridge die and a second contact on a second side of the bridge die, the recess extending to a first surface of the underlying substrate; a bond material to electrically and mechanically couple the first contact and an interconnect of the underlying substrate; and a fill material positioned between the first side of the bridge die and the first surface of the underlying substrate.

Abstract: Semiconductor chip package substrates having interconnect bridges, assemblies including these semiconductor chip package substrates, and methods of manufacturing interconnect-bridge-containing semiconductor package chip substrates are provided. The interconnect bridges can include through-bridge vias that are electrically coupled to the semiconductor package substrate. The embedded bridges can be aligned to fiducials within the semiconductor package substrate.

Abstract: Embodiments disclosed herein include apparatuses with assemblies comprising passive electrical devices that are embedded in a core of a package substrate. In an embodiment, such an apparatus may comprise a substrate with a first surface, a second surface opposite from the first surface, and a sidewall surface coupling the first surface to the second surface. In an embodiment the substrate comprises a passive electrical device. In an embodiment, a pad is on the first surface of the substrate, and a layer contacts the substrate. In an embodiment, the layer directly contacts the first surface and the sidewall surface of the substrate.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a substrate having a material and conductive pathways through the material, wherein the material includes an organic dielectric material; and a microelectronic component having a first surface and an opposing second surface, wherein the first surface of the microelectronic component is electrically coupled to the conductive pathways in the material by interconnects, wherein the interconnects include solder and are surrounded by a capillary underfill material, and wherein the microelectronic component and the capillary underfill material are surrounded by the material of the substrate.

Abstract: Assemblies and methods of manufacturing assemblies comprising semiconductor chips and package substrates wherein the semiconductor chips are operably coupled to the package substrate through a solderless direct metal-to-metal bond region. The solderless direct metal-to-metal bond region also comprises a dielectric polymer. Package substrates can comprise interconnect bridges and the semiconductor chips can be operably coupled to the interconnect bridges and can also be operably coupled to each other through the interconnect bridges.

Abstract: Methods, systems, apparatus, and articles of manufacture to reduce intermetallic compound formation in integrated circuit packages are disclosed. An example package substrate includes a buildup layer including a metal pad, an interconnect bridge embedded in the buildup layer, the interconnect bridge including a first contact pad on a first side of the interconnect bridge and a second contact pad on a second side of the interconnect bridge, the second side opposite the first side, and solder positioned between the metal pad and the first contact pad, the solder to electrically couple the metal pad and the first contact pad, a weight percent of nickel in any layer of material between the metal pad and the first contact pad being less than a threshold.

Abstract: Embodiments disclosed herein include bridge structures for package substrates. In an embodiment, a package substrate comprises a substrate that is a dielectric material. In an embodiment, a cavity is formed into the substrate. A first pad is on a bottom surface of the cavity, and a die is at least partially in the cavity. In an embodiment, a via passes through at least a portion of a thickness of the die, and a second pad is on the die. In an embodiment, the second pad directly contacts the first pad, and the first pad is the only electrically conductive structure between the via and the second pad.

Abstract: Embodiments disclosed herein include package substrates with bridge dies. In an embodiment, an apparatus comprises a first layer that is a glass layer. A via is provided through the first layer, where the via is electrically conductive. In an embodiment, a second layer is over the first layer, and the second layer comprises an organic dielectric material. In an embodiment, a cavity is provided in the second layer, where the via is within a footprint of the cavity. In an embodiment, a die is in the cavity. In an embodiment, the die is electrically coupled to the via.

Abstract: Methods and apparatus to connect interconnect bridges to package substrates are disclosed. An example package substrate includes a dielectric layer including a cavity, a first contact pad positioned in the cavity, a first semiconductor die including a second contact pad and a third contact pad, the second contact pad positioned on a first surface of the first semiconductor die, the third contact pad positioned on a second surface of the first semiconductor die, the second surface opposite the first surface, the second contact pad coupled to the first contact pad, the third contact pad to be coupled to a second semiconductor die, and a non-conductive material surrounding the first contact pad and the second contact pad.

Abstract: An apparatus is provided which comprises: a plurality of interconnect layers within a substrate, organic dielectric material over the plurality of interconnect layers, copper pads on a surface of a cavity within the organic dielectric material, an integrated circuit bridge device coupled with the copper pads, wherein a surface of the integrated circuit bridge device is elevated above an opening of the cavity, underfill material between the integrated circuit bridge device and the surface of the cavity, and build-up layers formed over the organic dielectric material around the integrated circuit bridge device. Other embodiments are also disclosed and claimed.

Abstract: An electronic package comprises a substrate core; one or more dielectric material layers over the substrate core and having a lower dielectric material layer, and a plurality of metallization layers comprising an upper-most metallization layer; an integrated circuit (IC) die embedded within the dielectric material and below the upper-most metallization layer; and at least one conductive feature below and coupled to the IC die. A downwardly facing surface of the conductive feature is located on the lower dielectric material layer and defines a horizontal plane at a junction between the conductive feature and the lower dielectric material layer. The lower dielectric material layer has an upper facing surface facing in a direction of the IC die adjacent the conductive feature that is vertically offset from the horizontal plane.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer including first dies in a first insulating material; a second layer on the first layer, the second layer including second dies and third dies in a second insulating material, the second dies having a first thickness, the third dies having a second thickness different than the first thickness, and the second dies and the third dies having a surface, wherein the surfaces of the second and third dies have a combined surface area between 3,000 square millimeters (mm2) and 9,000 mm2; and a redistribution layer (RDL) between the first layer and the second layer, the RDL including conductive pathways through the RDL, wherein the first dies are electrically coupled to the second dies and the third dies by the conductive pathways through the RDL and by interconnects.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer having first dies in a first insulating material; a second layer on the first layer, the second layer including second dies having a first thickness and third dies having a second thickness different than the first thickness, the second dies and the third dies in a second insulating material, wherein the second dies and third dies have a first surface and an opposing second surface, and wherein the first surfaces of the second and third dies have a combined surface area between 3,000 square millimeters (mm2) and 9,000 mm2; and a redistribution layer (RDL) between the first layer and the second layer, the RDL including conductive pathways, wherein the first dies are electrically coupled to the second dies and the third dies by the conductive pathways and by interconnects.