Patents by Inventor MINGNI CHANG
MINGNI CHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240047345Abstract: A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a package structure. The package structure includes a passivation layer formed over an interconnect structure; an electrically-conductive structure formed on the passivation layer and extending through the passivation layer to electrically contact the interconnect structure; a dielectric structure formed over the passivation layer and surrounding the electrically-conductive structure to expose at least a portion of a top surface of the electrically-conductive structure; and a metallic protection structure formed on the top surface of the electrically-conductive structure exposed from the dielectric structure. The top surface of the metallic protection structure is aligned with or lower than a top surface of the dielectric structure.Type: ApplicationFiled: October 19, 2023Publication date: February 8, 2024Inventors: CHUN-WEI CHANG, HSUAN-MING HUANG, JIAN-HONG LIN, MING-HONG HSIEH, MINGNI CHANG, MING-YIH WANG
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Publication number: 20230411276Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method, and more particularly to a 3D metal insulator metal (MIM) capacitor structure. The MIM capacitor structure includes a first capacitor electrode formed on a top surface of a substrate, a dielectric layer formed on top and side surfaces of the first capacitor electrode and on the top surface of the substrate, and a second capacitor electrode formed on top and side surfaces of the dielectric layer. The first capacitor electrode has a first width. The second capacitor electrode has a second width greater than the first width.Type: ApplicationFiled: June 16, 2022Publication date: December 21, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ching-Jing Wu, Yun-Chin Tsou, An Shun Teng, Mingni Chang
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Patent number: 11830806Abstract: A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a package structure. The package structure includes a passivation layer formed over an interconnect structure; an electrically-conductive structure formed on the passivation layer and extending through the passivation layer to electrically contact the interconnect structure; a dielectric structure formed over the passivation layer and surrounding the electrically-conductive structure to expose at least a portion of a top surface of the electrically-conductive structure; and a metallic protection structure formed on the top surface of the electrically-conductive structure exposed from the dielectric structure. The top surface of the metallic protection structure is aligned with or lower than a top surface of the dielectric structure.Type: GrantFiled: April 29, 2021Date of Patent: November 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chun-Wei Chang, Hsuan-Ming Huang, Jian-Hong Lin, Ming-Hong Hsieh, Mingni Chang, Ming-Yih Wang
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Patent number: 11830832Abstract: A semiconductor structure is provided. The semiconductor structure includes a metallization structure with a dielectric surface. A first protecting structure over the dielectric surface. A first protecting structure over the passivation layer. A conductive pad over the dielectric surface. A polymer layer over the first protecting structure and the conductive pad. A conductive bump electrically coupled to the conductive pad through an opening of the polymer layer. A first portion of the first protecting structure is leveled with the conductive pad and a second portion of the first protecting structure is higher than the conductive pad.Type: GrantFiled: March 19, 2021Date of Patent: November 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tung-Jiun Wu, Mingni Chang, Ming-Yih Wang, Yinlung Lu
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Publication number: 20230290673Abstract: The present disclosure describes a structure with passivation layers with rounded corners and a method for forming such a structure. The method includes forming a first insulating layer on a substrate, where the substrate includes a first conductive structure. The method further includes forming an opening in the first insulating layer to expose the first conductive structure and forming a second conductive structure on the first insulating layer, where the second conductive structure is in contact with the first conductive structure through the opening.Type: ApplicationFiled: March 9, 2022Publication date: September 14, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mingni Chang, Hsuan-Ming HUANG
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Publication number: 20230005847Abstract: A method includes forming a plurality of low-k dielectric layers over a semiconductor substrate, forming a first plurality of dummy stacked structures extending into at least one of the plurality of low-k dielectric layers, forming a plurality of non-low-k dielectric layers over the plurality of low-k dielectric layers, and forming a second plurality of dummy stacked structures extending into the plurality of non-low-k dielectric layers. The second plurality of dummy stacked structures are over and connected to corresponding ones of the first plurality of dummy stacked structures. The method further includes etching the plurality of non-low-k dielectric layers, the plurality of low-k dielectric layers, and the semiconductor substrate to form a via opening. The via opening is encircled by the first plurality of dummy stacked structures and the second plurality of dummy stacked structures. The via opening is then filled to form a through-via.Type: ApplicationFiled: September 2, 2021Publication date: January 5, 2023Inventors: Mingni Chang, Yun-Chin Tsou, Ching-Jing Wu, Shiou-Fan Chen, Ming-Yih Wang
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Publication number: 20220406707Abstract: A method is provided for producing a semiconductor structure including at least one capacitor. The method includes: forming a first metal layer; forming a second metal layer; forming a third high resistance (HiR) layer interposed between the first metal layer and the second metal layer, wherein at least one of the first metal layer and the sconed metal layer at least partially overlap with the third HiR layer; and defining at least one of a first capacitor between the first metal layer and the third HiR layer and a second capacitor between the second metal layer and the third HiR layer. Suitably, the method is carried out subsequent to a front-end-of-line (FEOL) portion of a semiconductor fabrication process.Type: ApplicationFiled: February 9, 2022Publication date: December 22, 2022Inventors: Mingni Chang, Hsuan-Ming Huang, Shiou-Fan Chen
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Publication number: 20220352067Abstract: A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a package structure. The package structure includes a passivation layer formed over an interconnect structure; an electrically-conductive structure formed on the passivation layer and extending through the passivation layer to electrically contact the interconnect structure; a dielectric structure formed over the passivation layer and surrounding the electrically-conductive structure to expose at least a portion of a top surface of the electrically-conductive structure; and a metallic protection structure formed on the top surface of the electrically-conductive structure exposed from the dielectric structure. The top surface of the metallic protection structure is aligned with or lower than a top surface of the dielectric structure.Type: ApplicationFiled: April 29, 2021Publication date: November 3, 2022Inventors: CHUN-WEI CHANG, HSUAN-MING HUANG, JIAN-HONG LIN, MING-HONG HSIEH, MINGNI CHANG, MING-YIH WANG
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Publication number: 20220300695Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes receiving layout data representing information for manufacturing the semiconductor structure. A first parasitic capacitance is formed in a first region and a second parasitic capacitance is formed in a second region. The method further includes determining a parasitic capacitance difference between the first region and the second region; and forming a dummy conductor in the second region. A system for manufacturing a semiconductor device is also provided.Type: ApplicationFiled: June 10, 2022Publication date: September 22, 2022Inventors: HSUAN-MING HUANG, AN SHUN TENG, MINGNI CHANG, MING-YIH WANG, YINLUNG LU
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Patent number: 11361141Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes receiving layout data representing information for manufacturing the semiconductor structure having a metal layer over a substrate. A first parasitic capacitance and a second parasitic capacitance are formed between the metal layer and the substrate. The method further includes determining a parasitic capacitance difference between a first region and a second region. The method further includes forming a dummy capacitor to minimize the parasitic capacitance difference. A system for manufacturing a semiconductor device is also provided.Type: GrantFiled: July 27, 2020Date of Patent: June 14, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hsuan-Ming Huang, An Shun Teng, Mingni Chang, Ming-Yih Wang, Yinlung Lu
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Patent number: 11309258Abstract: A semiconductor structure includes a substrate, a MIM capacitor disposed over the substrate, a first insulating layer disposed over the MIM capacitor, an ONON stack disposed over the first insulating layer, a connecting via disposed in the first insulating layer, and a connecting pad disposed in the ONON stack and in contact with the connecting via. The ONON stack covers sidewalls of the connecting pad and a portion of a top surface of the connecting pad. The ONON stack includes a first silicon oxide layer, a first silicon nitride layer, a second silicon oxide layer and a second silicon nitride layer upwardly disposed over the first insulating layer. A thickness of the second silicon nitride layer is greater than a thickness of the second silicon oxide layer and greater than a thickness of the first silicon nitride layer.Type: GrantFiled: July 6, 2020Date of Patent: April 19, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tung-Jiun Wu, Yinlung Lu, Mingni Chang, Ming-Yih Wang
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Publication number: 20210210447Abstract: A semiconductor structure is provided. The semiconductor structure includes a metallization structure with a dielectric surface. A first protecting structure over the dielectric surface. A first protecting structure over the passivation layer. A conductive pad over the dielectric surface. A polymer layer over the first protecting structure and the conductive pad. A conductive bump electrically coupled to the conductive pad through an opening of the polymer layer. A first portion of the first protecting structure is leveled with the conductive pad and a second portion of the first protecting structure is higher than the conductive pad.Type: ApplicationFiled: March 19, 2021Publication date: July 8, 2021Inventors: TUNG-JIUN WU, MINGNI CHANG, MING-YIH WANG, YINLUNG LU
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Patent number: 10957664Abstract: A semiconductor structure and manufacturing method thereof are provided. The semiconductor structure includes a metallization structure with a dielectric surface. A first protecting structure is on the dielectric surface. A conductive pad is on the dielectric surface and is leveled with the first protecting structure. A polymer layer is over the first protecting structure and the conductive pad. A conductive bump is electrically coupled to the conductive pad through an opening of the polymer layer. A method for manufacturing a semiconductor structure is also provided.Type: GrantFiled: May 29, 2019Date of Patent: March 23, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tung-Jiun Wu, Mingni Chang, Ming-Yih Wang, Yinlung Lu
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Publication number: 20200402924Abstract: A semiconductor structure includes a substrate, a MIM capacitor disposed over the substrate, a first insulating layer disposed over the MIM capacitor, an ONON stack disposed over the first insulating layer, a connecting via disposed in the first insulating layer, and a connecting pad disposed in the ONON stack and in contact with the connecting via. The ONON stack covers sidewalls of the connecting pad and a portion of a top surface of the connecting pad. The ONON stack includes a first silicon oxide layer, a first silicon nitride layer, a second silicon oxide layer and a second silicon nitride layer upwardly disposed over the first insulating layer. A thickness of the second silicon nitride layer is greater than a thickness of the second silicon oxide layer and greater than a thickness of the first silicon nitride layer.Type: ApplicationFiled: July 6, 2020Publication date: December 24, 2020Inventors: TUNG-JIUN WU, YINLUNG LU, MINGNI CHANG, MING-YIH WANG
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Publication number: 20200381378Abstract: A semiconductor structure and manufacturing method thereof are provided. The semiconductor structure includes a metallization structure with a dielectric surface. A first protecting structure is on the dielectric surface. A conductive pad is on the dielectric surface and is leveled with the first protecting structure. A polymer layer is over the first protecting structure and the conductive pad. A conductive bump is electrically coupled to the conductive pad through an opening of the polymer layer. A method for manufacturing a semiconductor structure is also provided.Type: ApplicationFiled: May 29, 2019Publication date: December 3, 2020Inventors: TUNG-JIUN WU, MINGNI CHANG, MING-YIH WANG, YINLUNG LU
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Publication number: 20200356719Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes receiving a layout data representing information for manufacturing the semiconductor structure having a metal layer over a substrate. A first parasitic capacitance and a second parasitic capacitance are formed between the metal layer and the substrate. The method further includes determining a parasitic capacitance difference between a first region and a second region. The method further includes forming a dummy capacitor to minimize the parasitic capacitance difference. A system for manufacturing a semiconductor device is also provided.Type: ApplicationFiled: July 27, 2020Publication date: November 12, 2020Inventors: HSUAN-MING HUANG, AN SHUN TENG, MINGNI CHANG, MING-YIH WANG, YINLUNG LU
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Patent number: 10726191Abstract: The present disclosure provides a method for manufacturing a semiconductor device. The method includes receiving layout data representing mask information for manufacturing a semiconductive substrate with a conductor over the semiconductive substrate. A first capacitor is formed between the conductor and the semiconductive substrate. The method further includes determining a capacitance difference between capacitances of the first capacitor and a neighboring capacitor. The method further includes forming a dummy capacitor to minimize the capacitance difference. A system for manufacturing a semiconductor device is also provided.Type: GrantFiled: January 11, 2019Date of Patent: July 28, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hsuan-Ming Huang, An Shun Teng, Mingni Chang, Ming-Yih Wang, Yinlung Lu
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Patent number: 10707179Abstract: A semiconductor structure including a MIM capacitor includes a substrate, a MIM capacitor disposed over the substrate, a first insulating layer disposed over the MIM capacitor, an ONON stack disposed over the first insulating layer, a connecting via disposed in the first insulating layer, and a connecting pad disposed in the ONON stack and in contact with the connecting via. The ONON stack covers sidewalls of the connecting pad and a portion of a top surface of the connecting pad.Type: GrantFiled: June 24, 2019Date of Patent: July 7, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tung-Jiun Wu, Yinlung Lu, Mingni Chang, Ming-Yih Wang
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Publication number: 20200104456Abstract: The present disclosure provides a method for manufacturing a semiconductor device. The method includes receiving layout data representing mask information for manufacturing a semiconductive substrate with a conductor over the semiconductive substrate. A first capacitor is formed between the conductor and the semiconductive substrate. The method further includes determining a difference in capacitances of the first capacitor and a neighboring capacitor. The method further includes forming a dummy capacitor to minimize the capacitance difference. A system for manufacturing a semiconductor device is also provided.Type: ApplicationFiled: January 11, 2019Publication date: April 2, 2020Inventors: HSUAN-MING HUANG, AN SHUN TENG, MINGNI CHANG, MING-YIH WANG, YINLUNG LU